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https://github.com/xemu-project/xemu.git
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mmu-hash*: Clean up permission checking
Currently checking of PTE permission bits is split messily amongst
ppc_hash{32,64}_pp_check(), ppc_hash{32,64}_check_prot() and their callers.
This patch cleans this up to have the new function
ppc_hash{32,64}_pte_prot() compute the page permissions from the SLBE (for
64-bit) or segment register (32-bit) and the pte. A greatly simplified
version of the actual permissions check is then open coded in the callers.
The 32-bit version of ppc_hash32_pte_prot() is implemented in terms of
ppc_hash32_pp_prot(), a renamed and slightly cleaned up version of the old
ppc_hash32_pp_check(), which is also used for checking BAT permissions on
the 601.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
David Gibson
Alexander Graf
parent
e1a53ba2e0
commit
e01b444523
@ -47,69 +47,60 @@ struct mmu_ctx_hash32 {
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int key; /* Access key */
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};
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static int ppc_hash32_pp_check(int key, int pp, int nx)
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static int ppc_hash32_pp_prot(int key, int pp, int nx)
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{
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int access;
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int prot;
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/* Compute access rights */
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access = 0;
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if (key == 0) {
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switch (pp) {
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case 0x0:
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case 0x1:
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case 0x2:
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access |= PAGE_WRITE;
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/* No break here */
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case 0x3:
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access |= PAGE_READ;
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prot = PAGE_READ | PAGE_WRITE;
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break;
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case 0x3:
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prot = PAGE_READ;
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break;
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default:
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abort();
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}
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} else {
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switch (pp) {
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case 0x0:
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access = 0;
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prot = 0;
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break;
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case 0x1:
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case 0x3:
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access = PAGE_READ;
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prot = PAGE_READ;
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break;
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case 0x2:
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access = PAGE_READ | PAGE_WRITE;
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prot = PAGE_READ | PAGE_WRITE;
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break;
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default:
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abort();
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}
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}
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if (nx == 0) {
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access |= PAGE_EXEC;
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prot |= PAGE_EXEC;
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}
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return access;
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return prot;
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}
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static int ppc_hash32_check_prot(int prot, int rwx)
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static int ppc_hash32_pte_prot(CPUPPCState *env,
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target_ulong sr, ppc_hash_pte32_t pte)
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{
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int ret;
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unsigned pp, key;
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if (rwx == 2) {
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if (prot & PAGE_EXEC) {
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ret = 0;
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} else {
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ret = -2;
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}
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} else if (rwx) {
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if (prot & PAGE_WRITE) {
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ret = 0;
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} else {
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ret = -2;
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}
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} else {
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if (prot & PAGE_READ) {
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ret = 0;
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} else {
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ret = -2;
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}
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}
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key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
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pp = pte.pte1 & HPTE32_R_PP;
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return ret;
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return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));
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}
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static target_ulong hash32_bat_size(CPUPPCState *env,
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@ -160,7 +151,7 @@ static int hash32_bat_601_prot(CPUPPCState *env,
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} else {
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key = !!(batu & BATU32_601_KP);
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}
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return ppc_hash32_pp_check(key, pp, 0);
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return ppc_hash32_pp_prot(key, pp, 0);
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}
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static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
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@ -380,11 +371,10 @@ static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
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static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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target_ulong eaddr, int rwx)
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{
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int ret;
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target_ulong sr;
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bool nx;
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hwaddr pte_offset;
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ppc_hash_pte32_t pte;
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const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
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assert((rwx == 0) || (rwx == 1) || (rwx == 2));
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@ -400,7 +390,10 @@ static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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if (env->nb_BATs != 0) {
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ctx->raddr = ppc_hash32_bat_lookup(env, eaddr, rwx, &ctx->prot);
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if (ctx->raddr != -1) {
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return ppc_hash32_check_prot(ctx->prot, rwx);
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if (need_prot[rwx] & ~ctx->prot) {
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return -2;
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}
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return 0;
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}
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}
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@ -414,8 +407,7 @@ static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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}
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/* 5. Check for segment level no-execute violation */
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nx = !!(sr & SR32_NX);
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if ((rwx == 2) && nx) {
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if ((rwx == 2) && (sr & SR32_NX)) {
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return -3;
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}
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@ -427,34 +419,27 @@ static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
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/* 7. Check access permissions */
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ctx->key = (((sr & SR32_KP) && (msr_pr != 0)) ||
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((sr & SR32_KS) && (msr_pr == 0))) ? 1 : 0;
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int access, pp;
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ctx->prot = ppc_hash32_pte_prot(env, sr, pte);
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pp = pte.pte1 & HPTE32_R_PP;
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/* Compute access rights */
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access = ppc_hash32_pp_check(ctx->key, pp, nx);
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/* Keep the matching PTE informations */
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ctx->raddr = pte.pte1;
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ctx->prot = access;
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ret = ppc_hash32_check_prot(ctx->prot, rwx);
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if (ret) {
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if (need_prot[rwx] & ~ctx->prot) {
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/* Access right violation */
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LOG_MMU("PTE access rejected\n");
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return ret;
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return -2;
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}
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LOG_MMU("PTE access granted !\n");
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/* 8. Update PTE referenced and changed bits if necessary */
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if (ppc_hash32_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) {
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if (ppc_hash32_pte_update_flags(ctx, &pte.pte1, 0, rwx) == 1) {
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ppc_hash32_store_hpte1(env, pte_offset, pte.pte1);
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}
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return ret;
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/* Keep the matching PTE informations */
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ctx->raddr = pte.pte1;
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return 0;
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}
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hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
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@ -43,7 +43,6 @@
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struct mmu_ctx_hash64 {
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hwaddr raddr; /* Real address */
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int prot; /* Protection bits */
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int key; /* Access key */
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};
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/*
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@ -229,72 +228,55 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
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* 64-bit hash table MMU handling
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*/
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static int ppc_hash64_pp_check(int key, int pp, bool nx)
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static int ppc_hash64_pte_prot(CPUPPCState *env,
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ppc_slb_t *slb, ppc_hash_pte64_t pte)
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{
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int access;
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unsigned pp, key;
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/* Some pp bit combinations have undefined behaviour, so default
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* to no access in those cases */
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int prot = 0;
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key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
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: (slb->vsid & SLB_VSID_KS));
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pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
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/* Compute access rights */
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/* When pp is 4, 5 or 7, the result is undefined. Set it to noaccess */
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access = 0;
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if (key == 0) {
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switch (pp) {
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case 0x0:
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case 0x1:
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case 0x2:
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access |= PAGE_WRITE;
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/* No break here */
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prot = PAGE_READ | PAGE_WRITE;
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break;
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case 0x3:
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case 0x6:
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access |= PAGE_READ;
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prot = PAGE_READ;
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break;
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}
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} else {
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switch (pp) {
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case 0x0:
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case 0x6:
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access = 0;
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prot = 0;
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break;
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case 0x1:
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case 0x3:
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access = PAGE_READ;
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prot = PAGE_READ;
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break;
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case 0x2:
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access = PAGE_READ | PAGE_WRITE;
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prot = PAGE_READ | PAGE_WRITE;
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break;
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}
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}
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if (!nx) {
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access |= PAGE_EXEC;
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/* No execute if either noexec or guarded bits set */
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if (!(pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G)) {
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prot |= PAGE_EXEC;
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}
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return access;
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}
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static int ppc_hash64_check_prot(int prot, int rwx)
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{
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int ret;
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if (rwx == 2) {
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if (prot & PAGE_EXEC) {
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ret = 0;
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} else {
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ret = -2;
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}
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} else if (rwx == 1) {
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if (prot & PAGE_WRITE) {
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ret = 0;
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} else {
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ret = -2;
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}
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} else {
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if (prot & PAGE_READ) {
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ret = 0;
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} else {
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ret = -2;
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}
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}
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return ret;
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return prot;
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}
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static int ppc_hash64_pte_update_flags(struct mmu_ctx_hash64 *ctx,
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@ -407,11 +389,11 @@ static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
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static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
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target_ulong eaddr, int rwx)
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{
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int ret;
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ppc_slb_t *slb;
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hwaddr pte_offset;
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ppc_hash_pte64_t pte;
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int target_page_bits;
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const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
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assert((rwx == 0) || (rwx == 1) || (rwx == 2));
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@ -444,37 +426,26 @@ static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
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LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
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/* 5. Check access permissions */
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ctx->key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
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: (slb->vsid & SLB_VSID_KS));
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ctx->prot = ppc_hash64_pte_prot(env, slb, pte);
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int access, pp;
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bool nx;
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pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
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/* No execute if either noexec or guarded bits set */
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nx = (pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G);
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/* Compute access rights */
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access = ppc_hash64_pp_check(ctx->key, pp, nx);
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/* Keep the matching PTE informations */
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ctx->raddr = pte.pte1;
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ctx->prot = access;
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ret = ppc_hash64_check_prot(ctx->prot, rwx);
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if (ret) {
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if ((need_prot[rwx] & ~ctx->prot) != 0) {
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/* Access right violation */
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LOG_MMU("PTE access rejected\n");
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return ret;
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return -2;
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}
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LOG_MMU("PTE access granted !\n");
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/* 6. Update PTE referenced and changed bits if necessary */
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if (ppc_hash64_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) {
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if (ppc_hash64_pte_update_flags(ctx, &pte.pte1, 0, rwx) == 1) {
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ppc_hash64_store_hpte1(env, pte_offset, pte.pte1);
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}
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/* Keep the matching PTE informations */
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ctx->raddr = pte.pte1;
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/* We have a TLB that saves 4K pages, so let's
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* split a huge page to 4k chunks */
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target_page_bits = (slb->vsid & SLB_VSID_L)
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@ -483,7 +454,7 @@ static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
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ctx->raddr |= (eaddr & ((1 << target_page_bits) - 1))
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& TARGET_PAGE_MASK;
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}
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return ret;
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return 0;
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}
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hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
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