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target/avr: Add instruction translation - Register definitions
Start implementation of instructions by adding register definitions. Signed-off-by: Michael Rolnik <mrolnik@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Signed-off-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20200705140315.260514-11-huth@tuxfamily.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Michael Rolnik
Philippe Mathieu-Daudé
parent
84a71e9a44
commit
e03feba007
142
target/avr/translate.c
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142
target/avr/translate.c
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/*
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* QEMU AVR CPU
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*
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* Copyright (c) 2019-2020 Michael Rolnik
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qemu/qemu-print.h"
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#include "tcg/tcg.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "tcg/tcg-op.h"
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#include "exec/cpu_ldst.h"
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#include "exec/helper-proto.h"
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#include "exec/helper-gen.h"
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#include "exec/log.h"
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#include "exec/translator.h"
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#include "exec/gen-icount.h"
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/*
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* Define if you want a BREAK instruction translated to a breakpoint
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* Active debugging connection is assumed
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* This is for
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* https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests
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* tests
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*/
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#undef BREAKPOINT_ON_BREAK
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static TCGv cpu_pc;
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static TCGv cpu_Cf;
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static TCGv cpu_Zf;
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static TCGv cpu_Nf;
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static TCGv cpu_Vf;
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static TCGv cpu_Sf;
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static TCGv cpu_Hf;
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static TCGv cpu_Tf;
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static TCGv cpu_If;
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static TCGv cpu_rampD;
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static TCGv cpu_rampX;
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static TCGv cpu_rampY;
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static TCGv cpu_rampZ;
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static TCGv cpu_r[NUMBER_OF_CPU_REGISTERS];
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static TCGv cpu_eind;
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static TCGv cpu_sp;
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static TCGv cpu_skip;
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static const char reg_names[NUMBER_OF_CPU_REGISTERS][8] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
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};
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#define REG(x) (cpu_r[x])
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enum {
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DISAS_EXIT = DISAS_TARGET_0, /* We want return to the cpu main loop. */
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DISAS_LOOKUP = DISAS_TARGET_1, /* We have a variable condition exit. */
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DISAS_CHAIN = DISAS_TARGET_2, /* We have a single condition exit. */
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};
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typedef struct DisasContext DisasContext;
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/* This is the state at translation time. */
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struct DisasContext {
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TranslationBlock *tb;
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CPUAVRState *env;
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CPUState *cs;
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target_long npc;
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uint32_t opcode;
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/* Routine used to access memory */
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int memidx;
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int bstate;
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int singlestep;
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/*
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* some AVR instructions can make the following instruction to be skipped
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* Let's name those instructions
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* A - instruction that can skip the next one
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* B - instruction that can be skipped. this depends on execution of A
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* there are two scenarios
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* 1. A and B belong to the same translation block
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* 2. A is the last instruction in the translation block and B is the last
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*
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* following variables are used to simplify the skipping logic, they are
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* used in the following manner (sketch)
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*
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* TCGLabel *skip_label = NULL;
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* if (ctx.skip_cond != TCG_COND_NEVER) {
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* skip_label = gen_new_label();
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* tcg_gen_brcond_tl(skip_cond, skip_var0, skip_var1, skip_label);
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* }
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*
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* if (free_skip_var0) {
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* tcg_temp_free(skip_var0);
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* free_skip_var0 = false;
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* }
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*
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* translate(&ctx);
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*
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* if (skip_label) {
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* gen_set_label(skip_label);
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* }
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*/
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TCGv skip_var0;
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TCGv skip_var1;
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TCGCond skip_cond;
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bool free_skip_var0;
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};
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static bool avr_have_feature(DisasContext *ctx, int feature)
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{
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if (!avr_feature(ctx->env, feature)) {
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gen_helper_unsupported(cpu_env);
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ctx->bstate = DISAS_NORETURN;
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return false;
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}
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return true;
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}
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static bool decode_insn(DisasContext *ctx, uint16_t insn);
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#include "decode_insn.inc.c"
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