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Show size for unassigned accesses (Robert Reif)

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5436 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2008-10-06 18:46:28 +00:00
parent 35f4b58c7a
commit e18231a3ff
8 changed files with 72 additions and 33 deletions
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2
exec-all.h
View File

@ -331,7 +331,7 @@ static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
#if defined(TARGET_SPARC) || defined(TARGET_MIPS)
do_unassigned_access(addr, 0, 1, 0);
do_unassigned_access(addr, 0, 1, 0, 4);
#else
cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
#endif

62
exec.c
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@ -2302,10 +2302,30 @@ static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
#endif
#ifdef TARGET_SPARC
do_unassigned_access(addr, 0, 0, 0);
#elif defined(TARGET_CRIS)
do_unassigned_access(addr, 0, 0, 0);
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
do_unassigned_access(addr, 0, 0, 0, 1);
#endif
return 0;
}
static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
#endif
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
do_unassigned_access(addr, 0, 0, 0, 2);
#endif
return 0;
}
static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
#endif
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
do_unassigned_access(addr, 0, 0, 0, 4);
#endif
return 0;
}
@ -2315,23 +2335,41 @@ static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
#endif
#ifdef TARGET_SPARC
do_unassigned_access(addr, 1, 0, 0);
#elif defined(TARGET_CRIS)
do_unassigned_access(addr, 1, 0, 0);
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
do_unassigned_access(addr, 1, 0, 0, 1);
#endif
}
static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
#endif
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
do_unassigned_access(addr, 1, 0, 0, 2);
#endif
}
static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
#endif
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
do_unassigned_access(addr, 1, 0, 0, 4);
#endif
}
static CPUReadMemoryFunc *unassigned_mem_read[3] = {
unassigned_mem_readb,
unassigned_mem_readb,
unassigned_mem_readb,
unassigned_mem_readw,
unassigned_mem_readl,
};
static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
unassigned_mem_writeb,
unassigned_mem_writeb,
unassigned_mem_writeb,
unassigned_mem_writew,
unassigned_mem_writel,
};
static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr,

2
target-cris/cpu.h
View File

@ -168,7 +168,7 @@ void do_interrupt(CPUCRISState *env);
int cpu_cris_signal_handler(int host_signum, void *pinfo,
void *puc);
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
int is_asi);
int is_asi, int size);
enum {
CC_OP_DYNAMIC, /* Use env->cc_op */

6
target-cris/op_helper.c
View File

@ -237,10 +237,10 @@ void helper_rfn(void)
}
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
int is_asi)
int is_asi, int size)
{
D(printf("%s addr=%x w=%d ex=%d asi=%d\n",
__func__, addr, is_write, is_exec, is_asi));
D(printf("%s addr=%x w=%d ex=%d asi=%d, size=%d\n",
__func__, addr, is_write, is_exec, is_asi, size));
}
static void evaluate_flags_writeback(uint32_t flags)

2
target-mips/cpu.h
View File

@ -470,7 +470,7 @@ void r4k_do_tlbr (void);
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
int unused);
int unused, int size);
#define CPUState CPUMIPSState
#define cpu_init cpu_mips_init

2
target-mips/op_helper.c
View File

@ -1911,7 +1911,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
}
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
int unused)
int unused, int size)
{
if (is_exec)
do_raise_exception(EXCP_IBE);

2
target-sparc/cpu.h
View File

@ -430,7 +430,7 @@ static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
/* cpu-exec.c */
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
int is_asi);
int is_asi, int size);
int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
#define CPUState CPUSPARCState

27
target-sparc/op_helper.c
View File

@ -950,7 +950,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
break;
case 8: /* User code access, XXX */
default:
do_unassigned_access(addr, 0, 0, asi);
do_unassigned_access(addr, 0, 0, asi, size);
ret = 0;
break;
}
@ -1284,7 +1284,7 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
case 8: /* User code access, XXX */
case 9: /* Supervisor code access, XXX */
default:
do_unassigned_access(addr, 1, 0, asi);
do_unassigned_access(addr, 1, 0, asi, size);
break;
}
#ifdef DEBUG_ASI
@ -1464,7 +1464,7 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
case 0x8a: // Primary no-fault LE, RO
case 0x8b: // Secondary no-fault LE, RO
default:
do_unassigned_access(addr, 1, 0, 1);
do_unassigned_access(addr, 1, 0, 1, size);
return;
}
}
@ -1675,7 +1675,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
case 0x5f: // D-MMU demap, WO
case 0x77: // Interrupt vector, WO
default:
do_unassigned_access(addr, 0, 0, 1);
do_unassigned_access(addr, 0, 0, 1, size);
ret = 0;
break;
}
@ -2082,7 +2082,7 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
case 0x8a: // Primary no-fault LE, RO
case 0x8b: // Secondary no-fault LE, RO
default:
do_unassigned_access(addr, 1, 0, 1);
do_unassigned_access(addr, 1, 0, 1, size);
return;
}
}
@ -3025,7 +3025,7 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
#ifndef TARGET_SPARC64
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
int is_asi)
int is_asi, int size)
{
CPUState *saved_env;
@ -3035,14 +3035,15 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
env = cpu_single_env;
#ifdef DEBUG_UNASSIGNED
if (is_asi)
printf("Unassigned mem %s access to " TARGET_FMT_plx
printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
" asi 0x%02x from " TARGET_FMT_lx "\n",
is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi,
env->pc);
is_exec ? "exec" : is_write ? "write" : "read", size,
size == 1 ? "" : "s", addr, is_asi, env->pc);
else
printf("Unassigned mem %s access to " TARGET_FMT_plx " from "
TARGET_FMT_lx "\n",
is_exec ? "exec" : is_write ? "write" : "read", addr, env->pc);
printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
" from " TARGET_FMT_lx "\n",
is_exec ? "exec" : is_write ? "write" : "read", size,
size == 1 ? "" : "s", addr, env->pc);
#endif
if (env->mmuregs[3]) /* Fault status register */
env->mmuregs[3] = 1; /* overflow (not read before another fault) */
@ -3066,7 +3067,7 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
}
#else
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
int is_asi)
int is_asi, int size)
{
#ifdef DEBUG_UNASSIGNED
CPUState *saved_env;