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https://github.com/xemu-project/xemu.git
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plugins: Added a new cache modelling plugin
Added a cache modelling plugin that uses a static configuration used in many of the commercial microprocessors and uses random eviction policy. The purpose of the plugin is to identify the most cache-thrashing instructions for both instruction cache and data cache. Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210623125458.450462-2-ma.mandourr@gmail.com> Message-Id: <20210709143005.1554-37-alex.bennee@linaro.org>
This commit is contained in:
Mahmoud Mandour
Alex Bennée
parent
307ce0aaeb
commit
e2c5557ce1
@ -19,6 +19,7 @@ NAMES += hotpages
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NAMES += howvec
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NAMES += lockstep
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NAMES += hwprofile
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NAMES += cache
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SONAMES := $(addsuffix .so,$(addprefix lib,$(NAMES)))
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419
contrib/plugins/cache.c
Normal file
419
contrib/plugins/cache.c
Normal file
@ -0,0 +1,419 @@
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/*
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* Copyright (C) 2021, Mahmoud Mandour <ma.mandourr@gmail.com>
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*
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* License: GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include <inttypes.h>
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#include <stdio.h>
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#include <glib.h>
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#include <qemu-plugin.h>
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QEMU_PLUGIN_EXPORT int qemu_plugin_version = QEMU_PLUGIN_VERSION;
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static enum qemu_plugin_mem_rw rw = QEMU_PLUGIN_MEM_RW;
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static GHashTable *miss_ht;
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static GMutex mtx;
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static GRand *rng;
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static int limit;
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static bool sys;
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static uint64_t dmem_accesses;
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static uint64_t dmisses;
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static uint64_t imem_accesses;
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static uint64_t imisses;
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/*
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* A CacheSet is a set of cache blocks. A memory block that maps to a set can be
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* put in any of the blocks inside the set. The number of block per set is
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* called the associativity (assoc).
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*
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* Each block contains the the stored tag and a valid bit. Since this is not
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* a functional simulator, the data itself is not stored. We only identify
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* whether a block is in the cache or not by searching for its tag.
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*
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* In order to search for memory data in the cache, the set identifier and tag
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* are extracted from the address and the set is probed to see whether a tag
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* match occur.
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*
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* An address is logically divided into three portions: The block offset,
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* the set number, and the tag.
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*
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* The set number is used to identify the set in which the block may exist.
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* The tag is compared against all the tags of a set to search for a match. If a
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* match is found, then the access is a hit.
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*/
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typedef struct {
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uint64_t tag;
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bool valid;
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} CacheBlock;
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typedef struct {
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CacheBlock *blocks;
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} CacheSet;
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typedef struct {
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CacheSet *sets;
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int num_sets;
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int cachesize;
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int assoc;
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int blksize_shift;
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uint64_t set_mask;
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uint64_t tag_mask;
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} Cache;
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typedef struct {
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char *disas_str;
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const char *symbol;
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uint64_t addr;
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uint64_t dmisses;
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uint64_t imisses;
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} InsnData;
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Cache *dcache, *icache;
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static int pow_of_two(int num)
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{
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g_assert((num & (num - 1)) == 0);
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int ret = 0;
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while (num /= 2) {
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ret++;
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}
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return ret;
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}
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static inline uint64_t extract_tag(Cache *cache, uint64_t addr)
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{
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return addr & cache->tag_mask;
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}
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static inline uint64_t extract_set(Cache *cache, uint64_t addr)
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{
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return (addr & cache->set_mask) >> cache->blksize_shift;
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}
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static Cache *cache_init(int blksize, int assoc, int cachesize)
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{
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Cache *cache;
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int i;
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uint64_t blk_mask;
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cache = g_new(Cache, 1);
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cache->assoc = assoc;
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cache->cachesize = cachesize;
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cache->num_sets = cachesize / (blksize * assoc);
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cache->sets = g_new(CacheSet, cache->num_sets);
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cache->blksize_shift = pow_of_two(blksize);
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for (i = 0; i < cache->num_sets; i++) {
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cache->sets[i].blocks = g_new0(CacheBlock, assoc);
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}
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blk_mask = blksize - 1;
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cache->set_mask = ((cache->num_sets - 1) << cache->blksize_shift);
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cache->tag_mask = ~(cache->set_mask | blk_mask);
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return cache;
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}
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static int get_invalid_block(Cache *cache, uint64_t set)
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{
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int i;
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for (i = 0; i < cache->assoc; i++) {
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if (!cache->sets[set].blocks[i].valid) {
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return i;
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}
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}
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return -1;
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}
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static int get_replaced_block(Cache *cache)
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{
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return g_rand_int_range(rng, 0, cache->assoc);
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}
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static bool in_cache(Cache *cache, uint64_t addr)
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{
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int i;
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uint64_t tag, set;
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tag = extract_tag(cache, addr);
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set = extract_set(cache, addr);
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for (i = 0; i < cache->assoc; i++) {
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if (cache->sets[set].blocks[i].tag == tag &&
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cache->sets[set].blocks[i].valid) {
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return true;
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}
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}
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return false;
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}
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/**
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* access_cache(): Simulate a cache access
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* @cache: The cache under simulation
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* @addr: The address of the requested memory location
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*
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* Returns true if the requsted data is hit in the cache and false when missed.
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* The cache is updated on miss for the next access.
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*/
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static bool access_cache(Cache *cache, uint64_t addr)
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{
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uint64_t tag, set;
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int replaced_blk;
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if (in_cache(cache, addr)) {
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return true;
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}
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tag = extract_tag(cache, addr);
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set = extract_set(cache, addr);
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replaced_blk = get_invalid_block(cache, set);
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if (replaced_blk == -1) {
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replaced_blk = get_replaced_block(cache);
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}
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cache->sets[set].blocks[replaced_blk].tag = tag;
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cache->sets[set].blocks[replaced_blk].valid = true;
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return false;
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}
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static void vcpu_mem_access(unsigned int vcpu_index, qemu_plugin_meminfo_t info,
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uint64_t vaddr, void *userdata)
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{
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uint64_t effective_addr;
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struct qemu_plugin_hwaddr *hwaddr;
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InsnData *insn;
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g_mutex_lock(&mtx);
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hwaddr = qemu_plugin_get_hwaddr(info, vaddr);
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if (hwaddr && qemu_plugin_hwaddr_is_io(hwaddr)) {
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g_mutex_unlock(&mtx);
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return;
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}
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effective_addr = hwaddr ? qemu_plugin_hwaddr_phys_addr(hwaddr) : vaddr;
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if (!access_cache(dcache, effective_addr)) {
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insn = (InsnData *) userdata;
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insn->dmisses++;
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dmisses++;
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}
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dmem_accesses++;
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g_mutex_unlock(&mtx);
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}
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static void vcpu_insn_exec(unsigned int vcpu_index, void *userdata)
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{
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uint64_t insn_addr;
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InsnData *insn;
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g_mutex_lock(&mtx);
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insn_addr = ((InsnData *) userdata)->addr;
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if (!access_cache(icache, insn_addr)) {
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insn = (InsnData *) userdata;
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insn->imisses++;
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imisses++;
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}
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imem_accesses++;
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g_mutex_unlock(&mtx);
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}
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static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
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{
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size_t n_insns;
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size_t i;
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InsnData *data;
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n_insns = qemu_plugin_tb_n_insns(tb);
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for (i = 0; i < n_insns; i++) {
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struct qemu_plugin_insn *insn = qemu_plugin_tb_get_insn(tb, i);
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uint64_t effective_addr;
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if (sys) {
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effective_addr = (uint64_t) qemu_plugin_insn_haddr(insn);
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} else {
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effective_addr = (uint64_t) qemu_plugin_insn_vaddr(insn);
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}
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/*
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* Instructions might get translated multiple times, we do not create
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* new entries for those instructions. Instead, we fetch the same
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* entry from the hash table and register it for the callback again.
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*/
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g_mutex_lock(&mtx);
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data = g_hash_table_lookup(miss_ht, GUINT_TO_POINTER(effective_addr));
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if (data == NULL) {
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data = g_new0(InsnData, 1);
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data->disas_str = qemu_plugin_insn_disas(insn);
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data->symbol = qemu_plugin_insn_symbol(insn);
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data->addr = effective_addr;
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g_hash_table_insert(miss_ht, GUINT_TO_POINTER(effective_addr),
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(gpointer) data);
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}
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g_mutex_unlock(&mtx);
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qemu_plugin_register_vcpu_mem_cb(insn, vcpu_mem_access,
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QEMU_PLUGIN_CB_NO_REGS,
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rw, data);
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qemu_plugin_register_vcpu_insn_exec_cb(insn, vcpu_insn_exec,
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QEMU_PLUGIN_CB_NO_REGS, data);
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}
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}
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static void insn_free(gpointer data)
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{
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InsnData *insn = (InsnData *) data;
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g_free(insn->disas_str);
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g_free(insn);
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}
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static void cache_free(Cache *cache)
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{
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for (int i = 0; i < cache->num_sets; i++) {
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g_free(cache->sets[i].blocks);
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}
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g_free(cache->sets);
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g_free(cache);
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}
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static int dcmp(gconstpointer a, gconstpointer b)
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{
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InsnData *insn_a = (InsnData *) a;
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InsnData *insn_b = (InsnData *) b;
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return insn_a->dmisses < insn_b->dmisses ? 1 : -1;
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}
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static int icmp(gconstpointer a, gconstpointer b)
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{
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InsnData *insn_a = (InsnData *) a;
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InsnData *insn_b = (InsnData *) b;
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return insn_a->imisses < insn_b->imisses ? 1 : -1;
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}
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static void log_stats()
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{
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g_autoptr(GString) rep = g_string_new("");
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g_string_append_printf(rep,
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"Data accesses: %lu, Misses: %lu\nMiss rate: %lf%%\n\n",
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dmem_accesses,
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dmisses,
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((double) dmisses / (double) dmem_accesses) * 100.0);
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g_string_append_printf(rep,
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"Instruction accesses: %lu, Misses: %lu\nMiss rate: %lf%%\n\n",
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imem_accesses,
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imisses,
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((double) imisses / (double) imem_accesses) * 100.0);
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qemu_plugin_outs(rep->str);
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}
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static void log_top_insns()
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{
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int i;
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GList *curr, *miss_insns;
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InsnData *insn;
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miss_insns = g_hash_table_get_values(miss_ht);
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miss_insns = g_list_sort(miss_insns, dcmp);
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g_autoptr(GString) rep = g_string_new("");
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g_string_append_printf(rep, "%s", "address, data misses, instruction\n");
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for (curr = miss_insns, i = 0; curr && i < limit; i++, curr = curr->next) {
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insn = (InsnData *) curr->data;
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g_string_append_printf(rep, "0x%" PRIx64, insn->addr);
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if (insn->symbol) {
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g_string_append_printf(rep, " (%s)", insn->symbol);
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}
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g_string_append_printf(rep, ", %ld, %s\n", insn->dmisses,
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insn->disas_str);
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}
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miss_insns = g_list_sort(miss_insns, icmp);
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g_string_append_printf(rep, "%s", "\naddress, fetch misses, instruction\n");
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for (curr = miss_insns, i = 0; curr && i < limit; i++, curr = curr->next) {
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insn = (InsnData *) curr->data;
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g_string_append_printf(rep, "0x%" PRIx64, insn->addr);
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if (insn->symbol) {
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g_string_append_printf(rep, " (%s)", insn->symbol);
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}
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g_string_append_printf(rep, ", %ld, %s\n", insn->imisses,
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insn->disas_str);
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}
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qemu_plugin_outs(rep->str);
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g_list_free(miss_insns);
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}
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static void plugin_exit(qemu_plugin_id_t id, void *p)
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{
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log_stats();
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log_top_insns();
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cache_free(dcache);
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cache_free(icache);
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g_hash_table_destroy(miss_ht);
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}
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QEMU_PLUGIN_EXPORT
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int qemu_plugin_install(qemu_plugin_id_t id, const qemu_info_t *info,
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int argc, char **argv)
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{
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int i;
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int iassoc, iblksize, icachesize;
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int dassoc, dblksize, dcachesize;
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limit = 32;
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sys = info->system_emulation;
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dassoc = 8;
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dblksize = 64;
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dcachesize = dblksize * dassoc * 32;
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iassoc = 8;
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iblksize = 64;
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icachesize = iblksize * iassoc * 32;
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for (i = 0; i < argc; i++) {
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char *opt = argv[i];
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if (g_str_has_prefix(opt, "limit=")) {
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limit = g_ascii_strtoll(opt + 6, NULL, 10);
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} else {
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fprintf(stderr, "option parsing failed: %s\n", opt);
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return -1;
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}
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}
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dcache = cache_init(dblksize, dassoc, dcachesize);
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icache = cache_init(iblksize, iassoc, icachesize);
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rng = g_rand_new();
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qemu_plugin_register_vcpu_tb_trans_cb(id, vcpu_tb_trans);
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qemu_plugin_register_atexit_cb(id, plugin_exit, NULL);
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miss_ht = g_hash_table_new_full(NULL, g_direct_equal, NULL, insn_free);
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return 0;
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}
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