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hw/intc/arm_gicv3: Fix decoding of ID register range
The GIC ID registers cover an area 0x30 bytes in size (12 registers, 4 bytes each). We were incorrectly decoding only the first 0x20 bytes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190524124248.28394-2-peter.maydell@linaro.org
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@ -533,7 +533,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
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}
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return MEMTX_OK;
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}
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case GICD_IDREGS ... GICD_IDREGS + 0x1f:
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case GICD_IDREGS ... GICD_IDREGS + 0x2f:
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/* ID registers */
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*data = gicv3_idreg(offset - GICD_IDREGS);
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return MEMTX_OK;
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@ -744,7 +744,7 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr offset,
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gicd_write_irouter(s, attrs, irq, r);
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return MEMTX_OK;
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}
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case GICD_IDREGS ... GICD_IDREGS + 0x1f:
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case GICD_IDREGS ... GICD_IDREGS + 0x2f:
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case GICD_TYPER:
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case GICD_IIDR:
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/* RO registers, ignore the write */
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@ -233,7 +233,7 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset,
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}
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*data = cs->gicr_nsacr;
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return MEMTX_OK;
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case GICR_IDREGS ... GICR_IDREGS + 0x1f:
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case GICR_IDREGS ... GICR_IDREGS + 0x2f:
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*data = gicv3_idreg(offset - GICR_IDREGS);
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return MEMTX_OK;
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default:
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@ -363,7 +363,7 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
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return MEMTX_OK;
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case GICR_IIDR:
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case GICR_TYPER:
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case GICR_IDREGS ... GICR_IDREGS + 0x1f:
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case GICR_IDREGS ... GICR_IDREGS + 0x2f:
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/* RO registers, ignore the write */
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid guest write to RO register at offset "
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