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main cpu loop is target independent
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@238 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
1e5ffbedde
commit
e4533c7a8c
@ -17,18 +17,33 @@
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "config.h"
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#ifdef TARGET_I386
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#include "exec-i386.h"
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#endif
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#ifdef TARGET_ARM
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#include "exec-arm.h"
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#endif
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#include "disas.h"
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//#define DEBUG_EXEC
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//#define DEBUG_SIGNAL
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#if defined(TARGET_ARM)
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/* XXX: unify with i386 target */
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void cpu_loop_exit(void)
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{
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longjmp(env->jmp_env, 1);
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}
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#endif
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/* main execution loop */
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int cpu_x86_exec(CPUX86State *env1)
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int cpu_exec(CPUState *env1)
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{
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int saved_T0, saved_T1, saved_A0;
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CPUX86State *saved_env;
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int saved_T0, saved_T1, saved_T2;
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CPUState *saved_env;
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#ifdef reg_EAX
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int saved_EAX;
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#endif
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@ -65,9 +80,15 @@ int cpu_x86_exec(CPUX86State *env1)
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/* first we save global registers */
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saved_T0 = T0;
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saved_T1 = T1;
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saved_A0 = A0;
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saved_T2 = T2;
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saved_env = env;
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env = env1;
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#ifdef __sparc__
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/* we also save i7 because longjmp may not restore it */
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asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
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#endif
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#if defined(TARGET_I386)
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#ifdef reg_EAX
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saved_EAX = EAX;
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EAX = env->regs[R_EAX];
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@ -100,16 +121,24 @@ int cpu_x86_exec(CPUX86State *env1)
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saved_EDI = EDI;
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EDI = env->regs[R_EDI];
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#endif
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#ifdef __sparc__
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/* we also save i7 because longjmp may not restore it */
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asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
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#endif
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/* put eflags in CPU temporary format */
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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DF = 1 - (2 * ((env->eflags >> 10) & 1));
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CC_OP = CC_OP_EFLAGS;
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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#elif defined(TARGET_ARM)
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{
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unsigned int psr;
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psr = env->cpsr;
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env->CF = (psr >> 29) & 1;
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env->NZF = (psr & 0xc0000000) ^ 0x40000000;
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env->VF = (psr << 3) & 0x80000000;
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env->cpsr = psr & ~0xf0000000;
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}
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#else
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#error unsupported target CPU
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#endif
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env->interrupt_request = 0;
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/* prepare setjmp context for exception handling */
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@ -126,7 +155,7 @@ int cpu_x86_exec(CPUX86State *env1)
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}
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#ifdef DEBUG_EXEC
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if (loglevel) {
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/* XXX: save all volatile state in cpu state */
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#if defined(TARGET_I386)
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/* restore flags in standard format */
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env->regs[R_EAX] = EAX;
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env->regs[R_EBX] = EBX;
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@ -139,10 +168,16 @@ int cpu_x86_exec(CPUX86State *env1)
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env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
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cpu_x86_dump_state(env, logfile, 0);
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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#elif defined(TARGET_ARM)
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cpu_arm_dump_state(env, logfile, 0);
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#else
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#error unsupported target CPU
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#endif
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}
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#endif
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/* we compute the CPU state. We assume it will not
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change during the whole generated block. */
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#if defined(TARGET_I386)
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flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
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flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
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flags |= (((unsigned long)env->seg_cache[R_DS].base |
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@ -159,6 +194,13 @@ int cpu_x86_exec(CPUX86State *env1)
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flags |= (env->eflags & (IOPL_MASK | TF_MASK));
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cs_base = env->seg_cache[R_CS].base;
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pc = cs_base + env->eip;
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#elif defined(TARGET_ARM)
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flags = 0;
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cs_base = 0;
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pc = (uint8_t *)env->regs[15];
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#else
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#error unsupported CPU
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#endif
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tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
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flags);
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if (!tb) {
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@ -178,7 +220,9 @@ int cpu_x86_exec(CPUX86State *env1)
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tb->tc_ptr = tc_ptr;
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tb->cs_base = (unsigned long)cs_base;
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tb->flags = flags;
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ret = cpu_x86_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size);
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ret = cpu_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size);
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#if defined(TARGET_I386)
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/* XXX: suppress that, this is incorrect */
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/* if invalid instruction, signal it */
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if (ret != 0) {
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/* NOTE: the tb is allocated but not linked, so we
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@ -186,6 +230,7 @@ int cpu_x86_exec(CPUX86State *env1)
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spin_unlock(&tb_lock);
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raise_exception(EXCP06_ILLOP);
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}
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#endif
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*ptb = tb;
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tb->hash_next = NULL;
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tb_link(tb);
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@ -202,8 +247,12 @@ int cpu_x86_exec(CPUX86State *env1)
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#ifdef __sparc__
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T0 = tmp_T0;
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#endif
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/* see if we can patch the calling TB */
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if (T0 != 0 && !(env->eflags & TF_MASK)) {
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/* see if we can patch the calling TB. XXX: remove TF test */
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if (T0 != 0
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#if defined(TARGET_I386)
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&& !(env->eflags & TF_MASK)
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#endif
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) {
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spin_lock(&tb_lock);
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tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
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spin_unlock(&tb_lock);
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@ -232,6 +281,7 @@ int cpu_x86_exec(CPUX86State *env1)
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}
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ret = env->exception_index;
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#if defined(TARGET_I386)
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/* restore flags in standard format */
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env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
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@ -260,22 +310,34 @@ int cpu_x86_exec(CPUX86State *env1)
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#ifdef reg_EDI
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EDI = saved_EDI;
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#endif
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#elif defined(TARGET_ARM)
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{
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int ZF;
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ZF = (env->NZF == 0);
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env->cpsr = env->cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
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(env->CF << 29) | ((env->VF & 0x80000000) >> 3);
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}
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#else
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#error unsupported target CPU
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#endif
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#ifdef __sparc__
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asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
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#endif
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T0 = saved_T0;
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T1 = saved_T1;
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A0 = saved_A0;
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T2 = saved_T2;
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env = saved_env;
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return ret;
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}
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void cpu_x86_interrupt(CPUX86State *s)
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void cpu_interrupt(CPUState *s)
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{
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s->interrupt_request = 1;
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}
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#if defined(TARGET_I386)
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void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
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{
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CPUX86State *saved_env;
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@ -322,6 +384,8 @@ void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
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env = saved_env;
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}
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#endif /* TARGET_I386 */
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#undef EAX
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#undef ECX
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#undef EDX
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@ -357,15 +421,22 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
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if (tb) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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ret = cpu_x86_search_pc(tb, &found_pc, pc);
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ret = cpu_search_pc(tb, &found_pc, pc);
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if (ret < 0)
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return 0;
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#if defined(TARGET_I386)
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env->eip = found_pc - tb->cs_base;
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env->cr2 = address;
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/* we restore the process signal mask as the sigreturn should
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do it (XXX: use sigsetjmp) */
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sigprocmask(SIG_SETMASK, old_set, NULL);
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raise_exception_err(EXCP0E_PAGE, 4 | (is_write << 1));
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#elif defined(TARGET_ARM)
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env->regs[15] = found_pc;
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/* XXX: do more */
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#else
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#error unsupported target CPU
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#endif
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/* never comes here */
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return 1;
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} else {
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@ -375,8 +446,8 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
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#if defined(__i386__)
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int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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void *puc)
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int cpu_signal_handler(int host_signum, struct siginfo *info,
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void *puc)
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{
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struct ucontext *uc = puc;
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unsigned long pc;
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@ -396,8 +467,8 @@ int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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#elif defined(__powerpc)
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int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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void *puc)
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int cpu_signal_handler(int host_signum, struct siginfo *info,
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void *puc)
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{
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struct ucontext *uc = puc;
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struct pt_regs *regs = uc->uc_mcontext.regs;
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@ -420,7 +491,7 @@ int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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#elif defined(__alpha__)
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int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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int cpu_signal_handler(int host_signum, struct siginfo *info,
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void *puc)
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{
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struct ucontext *uc = puc;
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@ -449,8 +520,8 @@ int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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}
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#elif defined(__sparc__)
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int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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void *puc)
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int cpu_signal_handler(int host_signum, struct siginfo *info,
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void *puc)
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{
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uint32_t *regs = (uint32_t *)(info + 1);
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void *sigmask = (regs + 20);
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@ -482,8 +553,8 @@ int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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#elif defined(__arm__)
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int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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void *puc)
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int cpu_signal_handler(int host_signum, struct siginfo *info,
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void *puc)
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{
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struct ucontext *uc = puc;
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unsigned long pc;
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