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target/arm: Use gvec for NEON_3R_LOGIC insns
Move expanders for VBSL, VBIT, and VBIF from translate-a64.c. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181011205206.3552-9-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
246fa4aca9
commit
eabcd6faa9
@ -10398,70 +10398,9 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
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}
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}
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static void gen_bsl_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
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{
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tcg_gen_xor_i64(rn, rn, rm);
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tcg_gen_and_i64(rn, rn, rd);
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tcg_gen_xor_i64(rd, rm, rn);
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}
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static void gen_bit_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
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{
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tcg_gen_xor_i64(rn, rn, rd);
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tcg_gen_and_i64(rn, rn, rm);
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tcg_gen_xor_i64(rd, rd, rn);
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}
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static void gen_bif_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
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{
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tcg_gen_xor_i64(rn, rn, rd);
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tcg_gen_andc_i64(rn, rn, rm);
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tcg_gen_xor_i64(rd, rd, rn);
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}
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static void gen_bsl_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
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{
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tcg_gen_xor_vec(vece, rn, rn, rm);
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tcg_gen_and_vec(vece, rn, rn, rd);
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tcg_gen_xor_vec(vece, rd, rm, rn);
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}
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static void gen_bit_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
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{
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tcg_gen_xor_vec(vece, rn, rn, rd);
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tcg_gen_and_vec(vece, rn, rn, rm);
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tcg_gen_xor_vec(vece, rd, rd, rn);
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}
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static void gen_bif_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
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{
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tcg_gen_xor_vec(vece, rn, rn, rd);
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tcg_gen_andc_vec(vece, rn, rn, rm);
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tcg_gen_xor_vec(vece, rd, rd, rn);
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}
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/* Logic op (opcode == 3) subgroup of C3.6.16. */
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static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
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{
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static const GVecGen3 bsl_op = {
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.fni8 = gen_bsl_i64,
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.fniv = gen_bsl_vec,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.load_dest = true
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};
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static const GVecGen3 bit_op = {
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.fni8 = gen_bit_i64,
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.fniv = gen_bit_vec,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.load_dest = true
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};
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static const GVecGen3 bif_op = {
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.fni8 = gen_bif_i64,
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.fniv = gen_bif_vec,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.load_dest = true
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};
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int rm = extract32(insn, 16, 5);
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@ -5262,14 +5262,6 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
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return 0;
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}
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/* Bitwise select. dest = c ? t : f. Clobbers T and F. */
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static void gen_neon_bsl(TCGv_i32 dest, TCGv_i32 t, TCGv_i32 f, TCGv_i32 c)
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{
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tcg_gen_and_i32(t, t, c);
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tcg_gen_andc_i32(f, f, c);
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tcg_gen_or_i32(dest, t, f);
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}
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static inline void gen_neon_narrow(int size, TCGv_i32 dest, TCGv_i64 src)
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{
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switch (size) {
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@ -5712,6 +5704,73 @@ static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn,
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return 1;
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}
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/*
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* Expanders for VBitOps_VBIF, VBIT, VBSL.
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*/
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static void gen_bsl_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
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{
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tcg_gen_xor_i64(rn, rn, rm);
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tcg_gen_and_i64(rn, rn, rd);
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tcg_gen_xor_i64(rd, rm, rn);
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}
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static void gen_bit_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
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{
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tcg_gen_xor_i64(rn, rn, rd);
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tcg_gen_and_i64(rn, rn, rm);
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tcg_gen_xor_i64(rd, rd, rn);
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}
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static void gen_bif_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
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{
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tcg_gen_xor_i64(rn, rn, rd);
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tcg_gen_andc_i64(rn, rn, rm);
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tcg_gen_xor_i64(rd, rd, rn);
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}
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static void gen_bsl_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
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{
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tcg_gen_xor_vec(vece, rn, rn, rm);
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tcg_gen_and_vec(vece, rn, rn, rd);
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tcg_gen_xor_vec(vece, rd, rm, rn);
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}
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static void gen_bit_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
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{
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tcg_gen_xor_vec(vece, rn, rn, rd);
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tcg_gen_and_vec(vece, rn, rn, rm);
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tcg_gen_xor_vec(vece, rd, rd, rn);
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}
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static void gen_bif_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
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{
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tcg_gen_xor_vec(vece, rn, rn, rd);
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tcg_gen_andc_vec(vece, rn, rn, rm);
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tcg_gen_xor_vec(vece, rd, rd, rn);
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}
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const GVecGen3 bsl_op = {
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.fni8 = gen_bsl_i64,
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.fniv = gen_bsl_vec,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.load_dest = true
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};
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const GVecGen3 bit_op = {
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.fni8 = gen_bit_i64,
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.fniv = gen_bit_vec,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.load_dest = true
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};
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const GVecGen3 bif_op = {
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.fni8 = gen_bif_i64,
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.fniv = gen_bif_vec,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.load_dest = true
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};
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/* Translate a NEON data processing instruction. Return nonzero if the
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instruction is invalid.
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We process data in a mixture of 32-bit and 64-bit chunks.
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@ -5721,13 +5780,14 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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{
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int op;
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int q;
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int rd, rn, rm;
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int rd, rn, rm, rd_ofs, rn_ofs, rm_ofs;
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int size;
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int shift;
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int pass;
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int count;
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int pairwise;
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int u;
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int vec_size;
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uint32_t imm, mask;
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TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5;
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TCGv_ptr ptr1, ptr2, ptr3;
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@ -5751,6 +5811,11 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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VFP_DREG_N(rn, insn);
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VFP_DREG_M(rm, insn);
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size = (insn >> 20) & 3;
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vec_size = q ? 16 : 8;
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rd_ofs = neon_reg_offset(rd, 0);
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rn_ofs = neon_reg_offset(rn, 0);
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rm_ofs = neon_reg_offset(rm, 0);
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if ((insn & (1 << 23)) == 0) {
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/* Three register same length. */
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op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
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@ -5841,8 +5906,51 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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q, rd, rn, rm);
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}
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return 1;
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case NEON_3R_LOGIC: /* Logic ops. */
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switch ((u << 2) | size) {
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case 0: /* VAND */
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tcg_gen_gvec_and(0, rd_ofs, rn_ofs, rm_ofs,
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vec_size, vec_size);
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break;
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case 1: /* VBIC */
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tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs,
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vec_size, vec_size);
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break;
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case 2:
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if (rn == rm) {
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/* VMOV */
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tcg_gen_gvec_mov(0, rd_ofs, rn_ofs, vec_size, vec_size);
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} else {
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/* VORR */
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tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs,
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vec_size, vec_size);
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}
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break;
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case 3: /* VORN */
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tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs,
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vec_size, vec_size);
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break;
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case 4: /* VEOR */
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tcg_gen_gvec_xor(0, rd_ofs, rn_ofs, rm_ofs,
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vec_size, vec_size);
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break;
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case 5: /* VBSL */
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tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,
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vec_size, vec_size, &bsl_op);
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break;
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case 6: /* VBIT */
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tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,
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vec_size, vec_size, &bit_op);
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break;
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case 7: /* VBIF */
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tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,
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vec_size, vec_size, &bif_op);
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break;
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}
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return 0;
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}
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if (size == 3 && op != NEON_3R_LOGIC) {
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if (size == 3) {
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/* 64-bit element instructions. */
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for (pass = 0; pass < (q ? 2 : 1); pass++) {
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neon_load_reg64(cpu_V0, rn + pass);
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@ -6000,40 +6108,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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case NEON_3R_VRHADD:
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GEN_NEON_INTEGER_OP(rhadd);
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break;
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case NEON_3R_LOGIC: /* Logic ops. */
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switch ((u << 2) | size) {
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case 0: /* VAND */
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tcg_gen_and_i32(tmp, tmp, tmp2);
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break;
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case 1: /* BIC */
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tcg_gen_andc_i32(tmp, tmp, tmp2);
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break;
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case 2: /* VORR */
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tcg_gen_or_i32(tmp, tmp, tmp2);
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break;
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case 3: /* VORN */
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tcg_gen_orc_i32(tmp, tmp, tmp2);
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break;
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case 4: /* VEOR */
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tcg_gen_xor_i32(tmp, tmp, tmp2);
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break;
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case 5: /* VBSL */
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tmp3 = neon_load_reg(rd, pass);
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gen_neon_bsl(tmp, tmp, tmp2, tmp3);
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tcg_temp_free_i32(tmp3);
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break;
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case 6: /* VBIT */
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tmp3 = neon_load_reg(rd, pass);
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gen_neon_bsl(tmp, tmp, tmp3, tmp2);
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tcg_temp_free_i32(tmp3);
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break;
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case 7: /* VBIF */
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tmp3 = neon_load_reg(rd, pass);
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gen_neon_bsl(tmp, tmp3, tmp, tmp2);
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tcg_temp_free_i32(tmp3);
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break;
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}
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break;
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case NEON_3R_VHSUB:
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GEN_NEON_INTEGER_OP(hsub);
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break;
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@ -191,6 +191,12 @@ static inline TCGv_i32 get_ahp_flag(void)
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return ret;
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}
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/* Vector operations shared between ARM and AArch64. */
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extern const GVecGen3 bsl_op;
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extern const GVecGen3 bit_op;
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extern const GVecGen3 bif_op;
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/*
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* Forward to the isar_feature_* tests given a DisasContext pointer.
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*/
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