ppc/spapr: Add FWNMI System Reset state

The FWNMI option must deliver system reset interrupts to their
registered address, and there are a few constraints on the handler
addresses specified in PAPR. Add the system reset address state and
checks.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20200316142613.121089-4-npiggin@gmail.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviwed-by: Mahesh Salgaonkar <mahesh@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Nicholas Piggin 2020-03-17 00:26:08 +10:00 committed by David Gibson
parent 8af7e1fe6f
commit edfdbf9c6b
3 changed files with 17 additions and 2 deletions

View File

@ -1688,6 +1688,7 @@ static void spapr_machine_reset(MachineState *machine)
spapr->cas_reboot = false; spapr->cas_reboot = false;
spapr->fwnmi_system_reset_addr = -1;
spapr->fwnmi_machine_check_addr = -1; spapr->fwnmi_machine_check_addr = -1;
spapr->fwnmi_machine_check_interlock = -1; spapr->fwnmi_machine_check_interlock = -1;
@ -2007,6 +2008,7 @@ static const VMStateDescription vmstate_spapr_fwnmi = {
.needed = spapr_fwnmi_needed, .needed = spapr_fwnmi_needed,
.pre_save = spapr_fwnmi_pre_save, .pre_save = spapr_fwnmi_pre_save,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState),
VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState),
VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()

View File

@ -414,6 +414,7 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu,
uint32_t nret, target_ulong rets) uint32_t nret, target_ulong rets)
{ {
hwaddr rtas_addr; hwaddr rtas_addr;
target_ulong sreset_addr, mce_addr;
if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_OFF) { if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_OFF) {
rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED);
@ -426,7 +427,18 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu,
return; return;
} }
spapr->fwnmi_machine_check_addr = rtas_ld(args, 1); sreset_addr = rtas_ld(args, 0);
mce_addr = rtas_ld(args, 1);
/* PAPR requires these are in the first 32M of memory and within RMA */
if (sreset_addr >= 32 * MiB || sreset_addr >= spapr->rma_size ||
mce_addr >= 32 * MiB || mce_addr >= spapr->rma_size) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
return;
}
spapr->fwnmi_system_reset_addr = sreset_addr;
spapr->fwnmi_machine_check_addr = mce_addr;
rtas_st(rets, 0, RTAS_OUT_SUCCESS); rtas_st(rets, 0, RTAS_OUT_SUCCESS);
} }

View File

@ -194,9 +194,10 @@ struct SpaprMachineState {
/* State related to FWNMI option */ /* State related to FWNMI option */
/* Machine Check Notification Routine address /* System Reset and Machine Check Notification Routine addresses
* registered by "ibm,nmi-register" RTAS call. * registered by "ibm,nmi-register" RTAS call.
*/ */
target_ulong fwnmi_system_reset_addr;
target_ulong fwnmi_machine_check_addr; target_ulong fwnmi_machine_check_addr;
/* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is