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ppc/spapr: Add FWNMI System Reset state
The FWNMI option must deliver system reset interrupts to their registered address, and there are a few constraints on the handler addresses specified in PAPR. Add the system reset address state and checks. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20200316142613.121089-4-npiggin@gmail.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviwed-by: Mahesh Salgaonkar <mahesh@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -1688,6 +1688,7 @@ static void spapr_machine_reset(MachineState *machine)
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spapr->cas_reboot = false;
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spapr->cas_reboot = false;
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spapr->fwnmi_system_reset_addr = -1;
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spapr->fwnmi_machine_check_addr = -1;
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spapr->fwnmi_machine_check_addr = -1;
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spapr->fwnmi_machine_check_interlock = -1;
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spapr->fwnmi_machine_check_interlock = -1;
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@ -2007,6 +2008,7 @@ static const VMStateDescription vmstate_spapr_fwnmi = {
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.needed = spapr_fwnmi_needed,
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.needed = spapr_fwnmi_needed,
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.pre_save = spapr_fwnmi_pre_save,
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.pre_save = spapr_fwnmi_pre_save,
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.fields = (VMStateField[]) {
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState),
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VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState),
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VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState),
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VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState),
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VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState),
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VMSTATE_END_OF_LIST()
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VMSTATE_END_OF_LIST()
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@ -414,6 +414,7 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu,
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uint32_t nret, target_ulong rets)
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uint32_t nret, target_ulong rets)
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{
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{
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hwaddr rtas_addr;
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hwaddr rtas_addr;
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target_ulong sreset_addr, mce_addr;
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if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_OFF) {
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if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_OFF) {
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rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED);
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rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED);
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@ -426,7 +427,18 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu,
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return;
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return;
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}
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}
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spapr->fwnmi_machine_check_addr = rtas_ld(args, 1);
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sreset_addr = rtas_ld(args, 0);
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mce_addr = rtas_ld(args, 1);
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/* PAPR requires these are in the first 32M of memory and within RMA */
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if (sreset_addr >= 32 * MiB || sreset_addr >= spapr->rma_size ||
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mce_addr >= 32 * MiB || mce_addr >= spapr->rma_size) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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spapr->fwnmi_system_reset_addr = sreset_addr;
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spapr->fwnmi_machine_check_addr = mce_addr;
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rtas_st(rets, 0, RTAS_OUT_SUCCESS);
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rtas_st(rets, 0, RTAS_OUT_SUCCESS);
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}
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}
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@ -194,9 +194,10 @@ struct SpaprMachineState {
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/* State related to FWNMI option */
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/* State related to FWNMI option */
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/* Machine Check Notification Routine address
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/* System Reset and Machine Check Notification Routine addresses
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* registered by "ibm,nmi-register" RTAS call.
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* registered by "ibm,nmi-register" RTAS call.
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*/
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*/
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target_ulong fwnmi_system_reset_addr;
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target_ulong fwnmi_machine_check_addr;
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target_ulong fwnmi_machine_check_addr;
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/* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is
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/* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is
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