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Host vector support for tcg/ppc.
Fix thread=single cpu kicking. -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAl2kgisdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/q+wgAoQQYDvjzdmZUyCFx DIf5FyRcx7bvrrWsfkRLs4Pwbo49LUcX400P/oZvGXs/ATiEmBTT+nSXWYBeLzY/ XeEhZM6U6lOkzqZF5RKdXpHb+YBe6HOQVpkKOSDlmf6H45B3J8lhten0pp0a2OK0 c3uxTQmR6uowbqWRwl3//pP98ynqjEmnrTh2+4fqF8idM5LlfGtlXA8Ga665RAYn TXcJ/bfDyRMTk1ubSxhTa8wiNxs8ihjrPNADbBQma4z6KgbhZ/1iMi8G82vcG3H3 qLAg7o9u2FUGxDo2tPyFSTpElvuf7XoNROQfvvSLEPCnhp3Xqt5mXRFxXFEnAsv1 RFHsyg== =pW3Z -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20191013' into staging Host vector support for tcg/ppc. Fix thread=single cpu kicking. # gpg: Signature made Mon 14 Oct 2019 15:11:55 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20191013: (23 commits) cpus: kick all vCPUs when running thread=single tcg/ppc: Update vector support for v3.00 dup/dupi tcg/ppc: Update vector support for v3.00 load/store tcg/ppc: Update vector support for v3.00 Altivec tcg/ppc: Update vector support for v2.07 FP tcg/ppc: Update vector support for v2.07 VSX tcg/ppc: Update vector support for v2.07 Altivec tcg/ppc: Update vector support for VSX tcg/ppc: Enable Altivec detection tcg/ppc: Support vector dup2 tcg/ppc: Support vector multiply tcg/ppc: Support vector shift by immediate tcg/ppc: Add support for vector saturated add/subtract tcg/ppc: Add support for vector add/subtract tcg/ppc: Add support for vector maximum/minimum tcg/ppc: Add support for load/store/logic/comparison tcg/ppc: Enable tcg backend vector compilation tcg/ppc: Replace HAVE_ISEL macro with a variable tcg/ppc: Replace HAVE_ISA_2_06 tcg/ppc: Create TCGPowerISA and have_isa ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
f22f553eff
24
cpus.c
24
cpus.c
@ -949,8 +949,8 @@ static inline int64_t qemu_tcg_next_kick(void)
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return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD;
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}
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/* Kick the currently round-robin scheduled vCPU */
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static void qemu_cpu_kick_rr_cpu(void)
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/* Kick the currently round-robin scheduled vCPU to next */
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static void qemu_cpu_kick_rr_next_cpu(void)
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{
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CPUState *cpu;
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do {
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@ -961,6 +961,16 @@ static void qemu_cpu_kick_rr_cpu(void)
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} while (cpu != atomic_mb_read(&tcg_current_rr_cpu));
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}
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/* Kick all RR vCPUs */
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static void qemu_cpu_kick_rr_cpus(void)
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{
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CPUState *cpu;
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CPU_FOREACH(cpu) {
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cpu_exit(cpu);
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};
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}
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static void do_nothing(CPUState *cpu, run_on_cpu_data unused)
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{
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}
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@ -993,7 +1003,7 @@ void qemu_timer_notify_cb(void *opaque, QEMUClockType type)
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static void kick_tcg_thread(void *opaque)
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{
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timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
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qemu_cpu_kick_rr_cpu();
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qemu_cpu_kick_rr_next_cpu();
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}
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static void start_tcg_kick_timer(void)
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@ -1827,9 +1837,11 @@ void qemu_cpu_kick(CPUState *cpu)
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{
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qemu_cond_broadcast(cpu->halt_cond);
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if (tcg_enabled()) {
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cpu_exit(cpu);
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/* NOP unless doing single-thread RR */
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qemu_cpu_kick_rr_cpu();
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if (qemu_tcg_mttcg_enabled()) {
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cpu_exit(cpu);
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} else {
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qemu_cpu_kick_rr_cpus();
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}
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} else {
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if (hax_enabled()) {
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/*
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@ -31,7 +31,7 @@
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# define TCG_TARGET_REG_BITS 32
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#endif
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#define TCG_TARGET_NB_REGS 32
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#define TCG_TARGET_NB_REGS 64
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
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@ -45,12 +45,33 @@ typedef enum {
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TCG_REG_R24, TCG_REG_R25, TCG_REG_R26, TCG_REG_R27,
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TCG_REG_R28, TCG_REG_R29, TCG_REG_R30, TCG_REG_R31,
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TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
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TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
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TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
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TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
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TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
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TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
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TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
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TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
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TCG_REG_CALL_STACK = TCG_REG_R1,
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TCG_AREG0 = TCG_REG_R27
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} TCGReg;
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extern bool have_isa_2_06;
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extern bool have_isa_3_00;
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typedef enum {
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tcg_isa_base,
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tcg_isa_2_06,
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tcg_isa_2_07,
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tcg_isa_3_00,
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} TCGPowerISA;
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extern TCGPowerISA have_isa;
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extern bool have_altivec;
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extern bool have_vsx;
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#define have_isa_2_06 (have_isa >= tcg_isa_2_06)
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#define have_isa_2_07 (have_isa >= tcg_isa_2_07)
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#define have_isa_3_00 (have_isa >= tcg_isa_3_00)
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/* optional instructions automatically implemented */
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#define TCG_TARGET_HAS_ext8u_i32 0 /* andi */
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@ -126,6 +147,30 @@ extern bool have_isa_3_00;
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#define TCG_TARGET_HAS_mulsh_i64 1
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#endif
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/*
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* While technically Altivec could support V64, it has no 64-bit store
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* instruction and substituting two 32-bit stores makes the generated
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* code quite large.
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*/
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#define TCG_TARGET_HAS_v64 have_vsx
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#define TCG_TARGET_HAS_v128 have_altivec
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#define TCG_TARGET_HAS_v256 0
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#define TCG_TARGET_HAS_andc_vec 1
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#define TCG_TARGET_HAS_orc_vec have_isa_2_07
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#define TCG_TARGET_HAS_not_vec 1
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#define TCG_TARGET_HAS_neg_vec have_isa_3_00
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#define TCG_TARGET_HAS_abs_vec 0
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#define TCG_TARGET_HAS_shi_vec 0
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#define TCG_TARGET_HAS_shs_vec 0
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#define TCG_TARGET_HAS_shv_vec 1
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#define TCG_TARGET_HAS_cmp_vec 1
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#define TCG_TARGET_HAS_mul_vec 1
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#define TCG_TARGET_HAS_sat_vec 1
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec have_vsx
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#define TCG_TARGET_HAS_cmpsel_vec 0
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void flush_icache_range(uintptr_t start, uintptr_t stop);
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void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
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File diff suppressed because it is too large
Load Diff
13
tcg/ppc/tcg-target.opc.h
Normal file
13
tcg/ppc/tcg-target.opc.h
Normal file
@ -0,0 +1,13 @@
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/*
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* Target-specific opcodes for host vector expansion. These will be
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* emitted by tcg_expand_vec_op. For those familiar with GCC internals,
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* consider these to be UNSPEC with names.
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*/
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DEF(ppc_mrgh_vec, 1, 2, 0, IMPLVEC)
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DEF(ppc_mrgl_vec, 1, 2, 0, IMPLVEC)
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DEF(ppc_msum_vec, 1, 3, 0, IMPLVEC)
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DEF(ppc_muleu_vec, 1, 2, 0, IMPLVEC)
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DEF(ppc_mulou_vec, 1, 2, 0, IMPLVEC)
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DEF(ppc_pkum_vec, 1, 2, 0, IMPLVEC)
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DEF(ppc_rotl_vec, 1, 2, 0, IMPLVEC)
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