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Bugfixes.

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Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging

Bugfixes.

# gpg: Signature made Thu 24 Mar 2022 17:44:49 GMT
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
  build: disable fcf-protection on -march=486 -m16
  target/i386: properly reset TSC on reset
  target/i386: tcg: high bits SSE cmp operation must be ignored
  configure: remove dead int128 test
  KVM: x86: workaround invalid CPUID[0xD,9] info on some AMD processors
  i386: Set MCG_STATUS_RIPV bit for mce SRAR error
  target/i386/kvm: Free xsave_buf when destroying vCPU

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2022-03-25 10:14:47 +00:00
commit f345abe365
7 changed files with 39 additions and 33 deletions
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18
configure vendored
View File

@ -2463,24 +2463,6 @@ else # "$safe_stack" = ""
fi
fi
########################################
# check if __[u]int128_t is usable.
int128=no
cat > $TMPC << EOF
__int128_t a;
__uint128_t b;
int main (void) {
a = a + b;
b = a * b;
a = a * a;
return 0;
}
EOF
if compile_prog "" "" ; then
int128=yes
fi
########################################
# check if ccache is interfering with
# semantic analysis of macros

4
pc-bios/optionrom/Makefile
View File

@ -14,6 +14,10 @@ cc-option = $(if $(shell $(CC) $1 -c -o /dev/null -xc /dev/null >/dev/null 2>&1
override CFLAGS += -march=i486 -Wall
# If -fcf-protection is enabled in flags or compiler defaults that will
# conflict with -march=i486
override CFLAGS += $(call cc-option, -fcf-protection=none)
# Flags for dependency generation
override CPPFLAGS += -MMD -MP -MT $@ -MF $(@D)/$(*F).d

17
target/i386/cpu.c
View File

@ -4981,8 +4981,8 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
return cpu_list;
}
static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
bool migratable_only)
uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
bool migratable_only)
{
FeatureWordInfo *wi = &feature_word_info[w];
uint64_t r = 0;
@ -5931,6 +5931,19 @@ static void x86_cpu_reset(DeviceState *dev)
env->xstate_bv = 0;
env->pat = 0x0007040600070406ULL;
if (kvm_enabled()) {
/*
* KVM handles TSC = 0 specially and thinks we are hot-plugging
* a new CPU, use 1 instead to force a reset.
*/
if (env->tsc != 0) {
env->tsc = 1;
}
} else {
env->tsc = 0;
}
env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;

4
target/i386/cpu.h
View File

@ -606,6 +606,8 @@ typedef enum FeatureWord {
} FeatureWord;
typedef uint64_t FeatureWordArray[FEATURE_WORDS];
uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
bool migratable_only);
/* cpuid_features bits */
#define CPUID_FP87 (1U << 0)
@ -1552,7 +1554,6 @@ typedef struct CPUArchState {
target_ulong kernelgsbase;
#endif
uint64_t tsc;
uint64_t tsc_adjust;
uint64_t tsc_deadline;
uint64_t tsc_aux;
@ -1706,6 +1707,7 @@ typedef struct CPUArchState {
int64_t tsc_khz;
int64_t user_tsc_khz; /* for sanity check only */
uint64_t apic_bus_freq;
uint64_t tsc;
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
void *xsave_buf;
uint32_t xsave_buf_len;

19
target/i386/kvm/kvm-cpu.c
View File

@ -99,13 +99,18 @@ static void kvm_cpu_xsave_init(void)
for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) {
ExtSaveArea *esa = &x86_ext_save_areas[i];
if (esa->size) {
host_cpuid(0xd, i, &eax, &ebx, &ecx, &edx);
if (eax != 0) {
assert(esa->size == eax);
esa->offset = ebx;
esa->ecx = ecx;
}
if (!esa->size) {
continue;
}
if ((x86_cpu_get_supported_feature_word(esa->feature, false) & esa->bits)
!= esa->bits) {
continue;
}
host_cpuid(0xd, i, &eax, &ebx, &ecx, &edx);
if (eax != 0) {
assert(esa->size == eax);
esa->offset = ebx;
esa->ecx = ecx;
}
}
}

4
target/i386/kvm/kvm.c
View File

@ -569,7 +569,7 @@ static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
if (code == BUS_MCEERR_AR) {
status |= MCI_STATUS_AR | 0x134;
mcg_status |= MCG_STATUS_EIPV;
mcg_status |= MCG_STATUS_RIPV | MCG_STATUS_EIPV;
} else {
status |= 0xc0;
mcg_status |= MCG_STATUS_RIPV;
@ -2081,6 +2081,8 @@ int kvm_arch_destroy_vcpu(CPUState *cs)
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
g_free(env->xsave_buf);
if (cpu->kvm_msr_buf) {
g_free(cpu->kvm_msr_buf);
cpu->kvm_msr_buf = NULL;

6
target/i386/tcg/translate.c
View File

@ -4509,10 +4509,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
sse_fn_ppi(s->ptr0, s->ptr1, tcg_const_i32(val));
break;
case 0xc2:
/* compare insns */
val = x86_ldub_code(env, s);
if (val >= 8)
goto unknown_op;
/* compare insns, bits 7:3 (7:5 for AVX) are ignored */
val = x86_ldub_code(env, s) & 7;
sse_fn_epp = sse_op_table4[val][b1];
tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);