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mips: fulong 2e: Renovate coding style
The script checkpatch.pl located in scripts folder was
used to detect all errors and warrnings in files:
hw/mips/mips_fulong2e.c
hw/isa/vt82c686.c
hw/pci-host/bonito.c
include/hw/isa/vt82c686.h
These mips Fulong 2E machine files were edited and
all the errors and warrings generated by the checkpatch.pl
script were corrected and then the script was
ran again to make sure there are no more errors and warnings.
Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1575640687-20744-6-git-send-email-Filip.Bozuta@rt-rk.com>
This commit is contained in:
Filip Bozuta
Aleksandar Markovic
parent
f48eefa202
commit
f3db354ca4
@ -27,7 +27,7 @@
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#include "qemu/timer.h"
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#include "exec/address-spaces.h"
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//#define DEBUG_VT82C686B
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/* #define DEBUG_VT82C686B */
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#ifdef DEBUG_VT82C686B
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#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
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@ -35,8 +35,7 @@
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#define DPRINTF(fmt, ...)
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#endif
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typedef struct SuperIOConfig
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{
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typedef struct SuperIOConfig {
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uint8_t config[0x100];
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uint8_t index;
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uint8_t data;
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@ -102,7 +101,7 @@ static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size)
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SuperIOConfig *superio_conf = opaque;
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DPRINTF("superio_ioport_readb address 0x%x\n", addr);
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return (superio_conf->config[superio_conf->index]);
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return superio_conf->config[superio_conf->index];
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}
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static const MemoryRegionOps superio_ops = {
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@ -143,7 +142,7 @@ static void vt82c686b_isa_reset(DeviceState *dev)
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}
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/* write config pci function0 registers. PCI-ISA bridge */
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static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
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static void vt82c686b_write_config(PCIDevice *d, uint32_t address,
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uint32_t val, int len)
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{
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VT82C686BState *vt686 = VT82C686B_DEVICE(d);
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@ -365,7 +364,7 @@ static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp)
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pci_set_long(pci_conf + 0x48, 0x00000001);
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/* SMB ports:0xeee0~0xeeef */
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s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
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s->smb_io_base = ((s->smb_io_base & 0xfff0) + 0x0);
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pci_conf[0x90] = s->smb_io_base | 1;
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pci_conf[0x91] = s->smb_io_base >> 8;
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pci_conf[0xd2] = 0x90;
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@ -462,16 +461,18 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
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wmask = d->wmask;
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for (i = 0x00; i < 0xff; i++) {
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if (i<=0x03 || (i>=0x08 && i<=0x3f)) {
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wmask[i] = 0x00;
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}
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if (i <= 0x03 || (i >= 0x08 && i <= 0x3f)) {
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wmask[i] = 0x00;
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}
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}
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memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops,
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&vt82c->superio_conf, "superio", 2);
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memory_region_set_enabled(&vt82c->superio, false);
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/* The floppy also uses 0x3f0 and 0x3f1.
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* But we do not emulate a floppy, so just set it here. */
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/*
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* The floppy also uses 0x3f0 and 0x3f1.
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* But we do not emulate a floppy, so just set it here.
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*/
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memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
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&vt82c->superio);
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}
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@ -14,7 +14,8 @@
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* fulong 2e mini pc has a bonito north bridge.
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*/
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/* what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
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/*
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* what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
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*
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* devfn pci_slot<<3 + funno
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* one pci bus can have 32 devices and each device can have 8 functions.
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@ -49,7 +50,7 @@
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#include "sysemu/runstate.h"
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#include "exec/address-spaces.h"
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//#define DEBUG_BONITO
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/* #define DEBUG_BONITO */
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#ifdef DEBUG_BONITO
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#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
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@ -60,45 +61,45 @@
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/* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/
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#define BONITO_BOOT_BASE 0x1fc00000
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#define BONITO_BOOT_SIZE 0x00100000
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#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
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#define BONITO_BOOT_TOP (BONITO_BOOT_BASE + BONITO_BOOT_SIZE - 1)
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#define BONITO_FLASH_BASE 0x1c000000
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#define BONITO_FLASH_SIZE 0x03000000
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#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
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#define BONITO_FLASH_TOP (BONITO_FLASH_BASE + BONITO_FLASH_SIZE - 1)
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#define BONITO_SOCKET_BASE 0x1f800000
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#define BONITO_SOCKET_SIZE 0x00400000
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#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
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#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE + BONITO_SOCKET_SIZE - 1)
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#define BONITO_REG_BASE 0x1fe00000
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#define BONITO_REG_SIZE 0x00040000
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#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1)
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#define BONITO_REG_TOP (BONITO_REG_BASE + BONITO_REG_SIZE - 1)
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#define BONITO_DEV_BASE 0x1ff00000
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#define BONITO_DEV_SIZE 0x00100000
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#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
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#define BONITO_DEV_TOP (BONITO_DEV_BASE + BONITO_DEV_SIZE - 1)
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#define BONITO_PCILO_BASE 0x10000000
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#define BONITO_PCILO_BASE_VA 0xb0000000
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#define BONITO_PCILO_SIZE 0x0c000000
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#define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
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#define BONITO_PCILO_TOP (BONITO_PCILO_BASE + BONITO_PCILO_SIZE - 1)
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#define BONITO_PCILO0_BASE 0x10000000
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#define BONITO_PCILO1_BASE 0x14000000
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#define BONITO_PCILO2_BASE 0x18000000
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#define BONITO_PCIHI_BASE 0x20000000
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#define BONITO_PCIHI_SIZE 0x20000000
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#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
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#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE - 1)
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#define BONITO_PCIIO_BASE 0x1fd00000
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#define BONITO_PCIIO_BASE_VA 0xbfd00000
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#define BONITO_PCIIO_SIZE 0x00010000
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#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
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#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE + BONITO_PCIIO_SIZE - 1)
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#define BONITO_PCICFG_BASE 0x1fe80000
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#define BONITO_PCICFG_SIZE 0x00080000
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#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
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#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE + BONITO_PCICFG_SIZE - 1)
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#define BONITO_PCICONFIGBASE 0x00
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#define BONITO_REGBASE 0x100
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#define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE+BONITO_REG_BASE)
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#define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE + BONITO_REG_BASE)
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#define BONITO_PCICONFIG_SIZE (0x100)
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#define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE+BONITO_REG_BASE)
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#define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE + BONITO_REG_BASE)
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#define BONITO_INTERNAL_REG_SIZE (0x70)
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#define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE)
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@ -111,7 +112,7 @@
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#define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */
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#define BONITO_BONGENCFG_OFFSET 0x4
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#define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET>>2) /*0x104 */
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#define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET >> 2) /*0x104 */
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/* 2. IO & IDE configuration */
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#define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */
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@ -177,15 +178,15 @@
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/* idsel BIT = pci slot number +12 */
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#define PCI_SLOT_BASE 12
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#define PCI_IDSEL_VIA686B_BIT (17)
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#define PCI_IDSEL_VIA686B (1<<PCI_IDSEL_VIA686B_BIT)
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#define PCI_IDSEL_VIA686B (1 << PCI_IDSEL_VIA686B_BIT)
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#define PCI_ADDR(busno,devno,funno,regno) \
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((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno))
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#define PCI_ADDR(busno , devno , funno , regno) \
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((((busno) << 16) & 0xff0000) + (((devno) << 11) & 0xf800) + \
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(((funno) << 8) & 0x700) + (regno))
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typedef struct BonitoState BonitoState;
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typedef struct PCIBonitoState
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{
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typedef struct PCIBonitoState {
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PCIDevice dev;
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BonitoState *pcihost;
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@ -239,7 +240,8 @@ static void bonito_writel(void *opaque, hwaddr addr,
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saddr = addr >> 2;
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DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr);
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DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n",
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addr, val, saddr);
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switch (saddr) {
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case BONITO_BONPONCFG:
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case BONITO_IODEVCFG:
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@ -363,7 +365,7 @@ static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr,
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return 0;
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}
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val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)];
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val = ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)];
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return val;
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}
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@ -377,7 +379,7 @@ static void bonito_ldma_writel(void *opaque, hwaddr addr,
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return;
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}
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((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff;
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((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)] = val & 0xffffffff;
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}
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static const MemoryRegionOps bonito_ldma_ops = {
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@ -400,7 +402,7 @@ static uint64_t bonito_cop_readl(void *opaque, hwaddr addr,
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return 0;
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}
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val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)];
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val = ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)];
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return val;
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}
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@ -414,7 +416,7 @@ static void bonito_cop_writel(void *opaque, hwaddr addr,
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return;
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}
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((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff;
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((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)] = val & 0xffffffff;
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}
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static const MemoryRegionOps bonito_cop_ops = {
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@ -446,7 +448,8 @@ static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
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cfgaddr = addr & 0xffff;
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cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16;
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idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET;
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idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >>
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BONITO_PCICONF_IDSEL_OFFSET;
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devno = ctz32(idsel);
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funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET;
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regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET;
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@ -550,7 +553,7 @@ static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
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}
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/* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
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static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num)
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static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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int slot;
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@ -618,7 +621,10 @@ static void bonito_realize(PCIDevice *dev, Error **errp)
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SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost);
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PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
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/* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */
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/*
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* Bonito North Bridge, built on FPGA,
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* VENDOR_ID/DEVICE_ID are "undefined"
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*/
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pci_config_set_prog_interface(dev->config, 0x00);
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/* set the north bridge register mapping */
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