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target/microblaze: Use env_cpu, env_archcpu

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Cleanup in the boilerplate that each target must define.
Replace mb_env_get_cpu with env_archcpu.  The combination
CPU(mb_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.

Move cpu_mmu_index below the include of "exec/cpu-all.h",
so that the definition of env_archcpu is available.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2019-03-22 18:27:36 -07:00
parent a8d92fd869
commit f5c7e93ad9
5 changed files with 20 additions and 26 deletions
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2
linux-user/microblaze/cpu_loop.c
View File

@ -23,7 +23,7 @@
void cpu_loop(CPUMBState *env)
{
CPUState *cs = CPU(mb_env_get_cpu(env));
CPUState *cs = env_cpu(env);
int trapnr, ret;
target_siginfo_t info;

35
target/microblaze/cpu.h
View File

@ -310,11 +310,6 @@ struct MicroBlazeCPU {
CPUMBState env;
};
static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env)
{
return container_of(env, MicroBlazeCPU, env);
}
#define ENV_OFFSET offsetof(MicroBlazeCPU, env)
void mb_cpu_do_interrupt(CPUState *cs);
@ -344,21 +339,6 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo,
#define MMU_USER_IDX 2
/* See NB_MMU_MODES further up the file. */
static inline int cpu_mmu_index (CPUMBState *env, bool ifetch)
{
MicroBlazeCPU *cpu = mb_env_get_cpu(env);
/* Are we in nommu mode?. */
if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) {
return MMU_NOMMU_IDX;
}
if (env->sregs[SR_MSR] & MSR_UM) {
return MMU_USER_IDX;
}
return MMU_KERNEL_IDX;
}
bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
@ -384,4 +364,19 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
MemTxResult response, uintptr_t retaddr);
#endif
static inline int cpu_mmu_index(CPUMBState *env, bool ifetch)
{
MicroBlazeCPU *cpu = env_archcpu(env);
/* Are we in nommu mode?. */
if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) {
return MMU_NOMMU_IDX;
}
if (env->sregs[SR_MSR] & MSR_UM) {
return MMU_USER_IDX;
}
return MMU_KERNEL_IDX;
}
#endif

5
target/microblaze/mmu.c
View File

@ -34,7 +34,7 @@ static unsigned int tlb_decode_size(unsigned int f)
static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
{
CPUState *cs = CPU(mb_env_get_cpu(env));
CPUState *cs = env_cpu(env);
struct microblaze_mmu *mmu = &env->mmu;
unsigned int tlb_size;
uint32_t tlb_tag, end, t;
@ -228,7 +228,6 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn)
void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
{
MicroBlazeCPU *cpu = mb_env_get_cpu(env);
uint64_t tmp64;
unsigned int i;
qemu_log_mask(CPU_LOG_MMU,
@ -269,7 +268,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
/* Changes to the zone protection reg flush the QEMU TLB.
Fortunately, these are very uncommon. */
if (v != env->mmu.regs[rn]) {
tlb_flush(CPU(cpu));
tlb_flush(env_cpu(env));
}
env->mmu.regs[rn] = v;
break;

2
target/microblaze/op_helper.c
View File

@ -65,7 +65,7 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl)
void helper_raise_exception(CPUMBState *env, uint32_t index)
{
CPUState *cs = CPU(mb_env_get_cpu(env));
CPUState *cs = env_cpu(env);
cs->exception_index = index;
cpu_loop_exit(cs);

2
target/microblaze/translate.c
View File

@ -1604,7 +1604,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
{
CPUMBState *env = cs->env_ptr;
MicroBlazeCPU *cpu = mb_env_get_cpu(env);
MicroBlazeCPU *cpu = env_archcpu(env);
uint32_t pc_start;
struct DisasContext ctx;
struct DisasContext *dc = &ctx;