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target/loongarch: Add LoongArch interrupt and exception handle
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-24-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Xiaojuan Yang
Richard Henderson
parent
7e1c521e2a
commit
f757a2cd69
@ -80,6 +80,215 @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
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env->pc = value;
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}
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void loongarch_cpu_set_irq(void *opaque, int irq, int level)
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{
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LoongArchCPU *cpu = opaque;
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CPULoongArchState *env = &cpu->env;
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CPUState *cs = CPU(cpu);
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if (irq < 0 || irq >= N_IRQS) {
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return;
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}
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env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);
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if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env)
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{
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bool ret = 0;
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ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) &&
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!(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)));
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return ret;
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}
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/* Check if there is pending and not masked out interrupt */
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static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env)
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{
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uint32_t pending;
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uint32_t status;
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bool r;
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pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
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status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);
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r = (pending & status) != 0;
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return r;
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}
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static void loongarch_cpu_do_interrupt(CPUState *cs)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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bool update_badinstr = 1;
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int cause = -1;
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const char *name;
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bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR);
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uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS);
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if (cs->exception_index != EXCCODE_INT) {
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if (cs->exception_index < 0 ||
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cs->exception_index > ARRAY_SIZE(excp_names)) {
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name = "unknown";
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} else {
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name = excp_names[cs->exception_index];
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}
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qemu_log_mask(CPU_LOG_INT,
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"%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx
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" TLBRERA " TARGET_FMT_lx " %s exception\n", __func__,
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env->pc, env->CSR_ERA, env->CSR_TLBRERA, name);
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}
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switch (cs->exception_index) {
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case EXCCODE_DBP:
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env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1);
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env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC);
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goto set_DERA;
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set_DERA:
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env->CSR_DERA = env->pc;
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env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1);
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env->pc = env->CSR_EENTRY + 0x480;
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break;
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case EXCCODE_INT:
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if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
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env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1);
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goto set_DERA;
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}
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QEMU_FALLTHROUGH;
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case EXCCODE_PIF:
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cause = cs->exception_index;
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update_badinstr = 0;
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break;
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case EXCCODE_ADEM:
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case EXCCODE_SYS:
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case EXCCODE_BRK:
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case EXCCODE_PIL:
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case EXCCODE_PIS:
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case EXCCODE_PME:
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case EXCCODE_PNR:
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case EXCCODE_PNX:
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case EXCCODE_PPI:
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case EXCCODE_INE:
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case EXCCODE_IPE:
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case EXCCODE_FPE:
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cause = cs->exception_index;
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break;
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default:
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qemu_log("Error: exception(%d) '%s' has not been supported\n",
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cs->exception_index, excp_names[cs->exception_index]);
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abort();
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}
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if (update_badinstr) {
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env->CSR_BADI = cpu_ldl_code(env, env->pc);
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}
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/* Save PLV and IE */
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if (tlbfill) {
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env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV,
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FIELD_EX64(env->CSR_CRMD,
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CSR_CRMD, PLV));
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env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE,
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FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
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/* set the DA mode */
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
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env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
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PC, (env->pc >> 2));
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} else {
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env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, cause);
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env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
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FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
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env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
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FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
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env->CSR_ERA = env->pc;
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}
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
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if (cs->exception_index == EXCCODE_INT) {
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/* Interrupt */
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uint32_t vector = 0;
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uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
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pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);
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/* Find the highest-priority interrupt. */
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vector = 31 - clz32(pending);
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env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size;
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qemu_log_mask(CPU_LOG_INT,
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"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
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" cause %d\n" " A " TARGET_FMT_lx " D "
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TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS"
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TARGET_FMT_lx "\n",
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__func__, env->pc, env->CSR_ERA,
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cause, env->CSR_BADV, env->CSR_DERA, vector,
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env->CSR_ECFG, env->CSR_ESTAT);
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} else {
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if (tlbfill) {
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env->pc = env->CSR_TLBRENTRY;
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} else {
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env->pc = env->CSR_EENTRY;
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env->pc += cause * vec_size;
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}
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qemu_log_mask(CPU_LOG_INT,
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"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
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" cause %d%s\n, ESTAT " TARGET_FMT_lx
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" EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx
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"BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu
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" cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc,
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tlbfill ? env->CSR_TLBRERA : env->CSR_ERA,
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cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT,
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env->CSR_ECFG,
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tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV,
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env->CSR_BADI, env->gpr[11], cs->cpu_index,
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env->CSR_ASID);
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}
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cs->exception_index = -1;
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}
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static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
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vaddr addr, unsigned size,
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MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response,
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uintptr_t retaddr)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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if (access_type == MMU_INST_FETCH) {
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do_raise_exception(env, EXCCODE_ADEF, retaddr);
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} else {
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do_raise_exception(env, EXCCODE_ADEM, retaddr);
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}
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}
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static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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if (cpu_loongarch_hw_interrupts_enabled(env) &&
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cpu_loongarch_hw_interrupts_pending(env)) {
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/* Raise it */
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cs->exception_index = EXCCODE_INT;
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loongarch_cpu_do_interrupt(cs);
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return true;
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}
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}
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return false;
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}
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#ifdef CONFIG_TCG
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static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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@ -91,6 +300,20 @@ static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
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}
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#endif /* CONFIG_TCG */
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static bool loongarch_cpu_has_work(CPUState *cs)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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bool has_work = false;
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if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
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cpu_loongarch_hw_interrupts_pending(env)) {
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has_work = true;
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}
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return has_work;
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}
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static void loongarch_la464_initfn(Object *obj)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(obj);
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@ -237,6 +460,8 @@ static void loongarch_cpu_reset(DeviceState *dev)
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env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0);
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}
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env->pc = 0x1c000000;
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restore_fp_status(env);
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cs->exception_index = -1;
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}
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@ -269,6 +494,7 @@ static void loongarch_cpu_init(Object *obj)
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LoongArchCPU *cpu = LOONGARCH_CPU(obj);
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cpu_set_cpustate_pointers(cpu);
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qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS);
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}
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static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model)
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@ -337,6 +563,9 @@ static struct TCGCPUOps loongarch_tcg_ops = {
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.synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
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.tlb_fill = loongarch_cpu_tlb_fill,
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.cpu_exec_interrupt = loongarch_cpu_exec_interrupt,
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.do_interrupt = loongarch_cpu_do_interrupt,
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.do_transaction_failed = loongarch_cpu_do_transaction_failed,
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};
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#endif /* CONFIG_TCG */
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@ -357,6 +586,7 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
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device_class_set_parent_reset(dc, loongarch_cpu_reset, &lacc->parent_reset);
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cc->class_by_name = loongarch_cpu_class_by_name;
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cc->has_work = loongarch_cpu_has_work;
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cc->dump_state = loongarch_cpu_dump_state;
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cc->set_pc = loongarch_cpu_set_pc;
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dc->vmsd = &vmstate_loongarch_cpu;
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@ -184,6 +184,8 @@ FIELD(CSR_CRMD, WE, 9, 1)
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extern const char * const regnames[32];
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extern const char * const fregnames[32];
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#define N_IRQS 13
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#define LOONGARCH_STLB 2048 /* 2048 STLB */
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#define LOONGARCH_MTLB 64 /* 64 MTLB */
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#define LOONGARCH_TLB_MAX (LOONGARCH_STLB + LOONGARCH_MTLB)
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@ -30,6 +30,8 @@ void restore_fp_status(CPULoongArchState *env);
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extern const VMStateDescription vmstate_loongarch_cpu;
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void loongarch_cpu_set_irq(void *opaque, int irq, int level);
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bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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