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target/riscv: Allow setting CPU feature from machine/device emulation
The machine or device emulation should be able to force set certain CPU features because: 1) We can have certain CPU features which are in-general optional but implemented by RISC-V CPUs on the machine. 2) We can have devices which require a certain CPU feature. For example, AIA IMSIC devices expect AIA CSRs implemented by RISC-V CPUs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20220204174700.534953-6-anup@brainfault.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -135,11 +135,6 @@ static void set_vext_version(CPURISCVState *env, int vext_ver)
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env->vext_ver = vext_ver;
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}
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static void set_feature(CPURISCVState *env, int feature)
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{
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env->features |= (1ULL << feature);
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}
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static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
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{
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#ifndef CONFIG_USER_ONLY
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@ -508,18 +503,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
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}
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if (cpu->cfg.mmu) {
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set_feature(env, RISCV_FEATURE_MMU);
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riscv_set_feature(env, RISCV_FEATURE_MMU);
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}
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if (cpu->cfg.pmp) {
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set_feature(env, RISCV_FEATURE_PMP);
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riscv_set_feature(env, RISCV_FEATURE_PMP);
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/*
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* Enhanced PMP should only be available
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* on harts with PMP support
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*/
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if (cpu->cfg.epmp) {
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set_feature(env, RISCV_FEATURE_EPMP);
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riscv_set_feature(env, RISCV_FEATURE_EPMP);
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}
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}
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@ -379,6 +379,11 @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
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return env->features & (1ULL << feature);
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}
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static inline void riscv_set_feature(CPURISCVState *env, int feature)
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{
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env->features |= (1ULL << feature);
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}
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#include "cpu_user.h"
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extern const char * const riscv_int_regnames[];
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