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OMAP LPGs (LED pulse generators).
OMAP MPUI bridge config register. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3710 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog
parent
d07b4d0ea7
commit
f9d43072e2
186
hw/omap.c
186
hw/omap.c
@ -4626,6 +4626,184 @@ void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave)
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slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0];
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}
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/* LED Pulse Generators */
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struct omap_lpg_s {
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target_phys_addr_t base;
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QEMUTimer *tm;
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uint8_t control;
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uint8_t power;
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int64_t on;
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int64_t period;
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int clk;
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int cycle;
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};
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static void omap_lpg_tick(void *opaque)
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{
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struct omap_lpg_s *s = opaque;
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if (s->cycle)
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qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->period - s->on);
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else
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qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->on);
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s->cycle = !s->cycle;
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printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off");
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}
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static void omap_lpg_update(struct omap_lpg_s *s)
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{
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int64_t on, period = 1, ticks = 1000;
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static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
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if (~s->control & (1 << 6)) /* LPGRES */
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on = 0;
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else if (s->control & (1 << 7)) /* PERM_ON */
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on = period;
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else {
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period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */
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256 / 32);
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on = (s->clk && s->power) ? muldiv64(ticks,
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per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
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}
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qemu_del_timer(s->tm);
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if (on == period && s->on < s->period)
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printf("%s: LED is on\n", __FUNCTION__);
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else if (on == 0 && s->on)
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printf("%s: LED is off\n", __FUNCTION__);
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else if (on && (on != s->on || period != s->period)) {
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s->cycle = 0;
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s->on = on;
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s->period = period;
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omap_lpg_tick(s);
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return;
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}
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s->on = on;
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s->period = period;
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}
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static void omap_lpg_reset(struct omap_lpg_s *s)
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{
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s->control = 0x00;
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s->power = 0x00;
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s->clk = 1;
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omap_lpg_update(s);
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}
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static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
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{
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struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
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int offset = addr & OMAP_MPUI_REG_MASK;
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switch (offset) {
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case 0x00: /* LCR */
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return s->control;
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case 0x04: /* PMR */
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return s->power;
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}
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OMAP_BAD_REG(addr);
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return 0;
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}
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static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
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int offset = addr & OMAP_MPUI_REG_MASK;
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switch (offset) {
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case 0x00: /* LCR */
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if (~value & (1 << 6)) /* LPGRES */
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omap_lpg_reset(s);
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s->control = value & 0xff;
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omap_lpg_update(s);
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return;
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case 0x04: /* PMR */
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s->power = value & 0x01;
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omap_lpg_update(s);
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return;
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default:
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OMAP_BAD_REG(addr);
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return;
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}
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}
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static CPUReadMemoryFunc *omap_lpg_readfn[] = {
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omap_lpg_read,
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omap_badwidth_read8,
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omap_badwidth_read8,
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};
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static CPUWriteMemoryFunc *omap_lpg_writefn[] = {
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omap_lpg_write,
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omap_badwidth_write8,
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omap_badwidth_write8,
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};
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static void omap_lpg_clk_update(void *opaque, int line, int on)
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{
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struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
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s->clk = on;
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omap_lpg_update(s);
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}
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struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
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{
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int iomemtype;
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struct omap_lpg_s *s = (struct omap_lpg_s *)
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qemu_mallocz(sizeof(struct omap_lpg_s));
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s->base = base;
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s->tm = qemu_new_timer(rt_clock, omap_lpg_tick, s);
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omap_lpg_reset(s);
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iomemtype = cpu_register_io_memory(0, omap_lpg_readfn,
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omap_lpg_writefn, s);
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cpu_register_physical_memory(s->base, 0x800, iomemtype);
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omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
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return s;
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}
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/* MPUI Peripheral Bridge configuration */
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static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
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{
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if (addr == OMAP_MPUI_BASE) /* CMR */
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return 0xfe4d;
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OMAP_BAD_REG(addr);
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return 0;
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}
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static CPUReadMemoryFunc *omap_mpui_io_readfn[] = {
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omap_badwidth_read16,
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omap_mpui_io_read,
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omap_badwidth_read16,
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};
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static CPUWriteMemoryFunc *omap_mpui_io_writefn[] = {
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omap_badwidth_write16,
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omap_badwidth_write16,
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omap_badwidth_write16,
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};
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static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)
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{
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int iomemtype = cpu_register_io_memory(0, omap_mpui_io_readfn,
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omap_mpui_io_writefn, mpu);
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cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
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}
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/* General chip reset */
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static void omap_mpu_reset(void *opaque)
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{
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@ -4663,6 +4841,8 @@ static void omap_mpu_reset(void *opaque)
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omap_mcbsp_reset(mpu->mcbsp1);
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omap_mcbsp_reset(mpu->mcbsp2);
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omap_mcbsp_reset(mpu->mcbsp3);
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omap_lpg_reset(mpu->led[0]);
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omap_lpg_reset(mpu->led[1]);
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cpu_reset(mpu->env);
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}
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@ -4846,6 +5026,9 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
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s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
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&s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
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s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz"));
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s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz"));
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/* Register mappings not currenlty implemented:
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* MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
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* MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
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@ -4855,8 +5038,6 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
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* FAC fffba800 - fffbafff
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* HDQ/1-Wire fffbc000 - fffbc7ff
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* TIPB switches fffbc800 - fffbcfff
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* LED1 fffbd000 - fffbd7ff
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* LED2 fffbd800 - fffbdfff
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* Mailbox fffcf000 - fffcf7ff
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* Local bus IF fffec100 - fffec1ff
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* Local bus MMU fffec200 - fffec2ff
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@ -4864,6 +5045,7 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
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*/
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omap_setup_dsp_mapping(omap15xx_dsp_mm);
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omap_setup_mpui_io(s);
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qemu_register_reset(omap_mpu_reset, s);
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@ -508,6 +508,9 @@ struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
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qemu_irq *irq, qemu_irq *dma, omap_clk clk);
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void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave);
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struct omap_lpg_s;
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struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
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/* omap_lcdc.c */
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struct omap_lcd_panel_s;
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void omap_lcdc_reset(struct omap_lcd_panel_s *s);
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@ -598,6 +601,8 @@ struct omap_mpu_state_s {
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struct omap_mcbsp_s *mcbsp2;
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struct omap_lpg_s *led[2];
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/* MPU private TIPB peripherals */
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struct omap_intr_handler_s *ih[2];
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