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tcg: Add EXCP_ATOMIC
When we cannot emulate an atomic operation within a parallel context, this exception allows us to stop the world and try again in a serial context. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
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1edaeee095
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fdbc2b5722
@ -77,3 +77,9 @@ void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc)
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}
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siglongjmp(cpu->jmp_env, 1);
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}
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void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc)
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{
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cpu->exception_index = EXCP_ATOMIC;
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cpu_loop_exit_restore(cpu, pc);
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}
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30
cpu-exec.c
30
cpu-exec.c
@ -222,6 +222,36 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
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}
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#endif
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static void cpu_exec_step(CPUState *cpu)
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{
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CPUArchState *env = (CPUArchState *)cpu->env_ptr;
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TranslationBlock *tb;
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target_ulong cs_base, pc;
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uint32_t flags;
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cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
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tb = tb_gen_code(cpu, pc, cs_base, flags,
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1 | CF_NOCACHE | CF_IGNORE_ICOUNT);
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tb->orig_tb = NULL;
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/* execute the generated code */
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trace_exec_tb_nocache(tb, pc);
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cpu_tb_exec(cpu, tb);
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tb_phys_invalidate(tb, -1);
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tb_free(tb);
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}
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void cpu_exec_step_atomic(CPUState *cpu)
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{
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start_exclusive();
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/* Since we got here, we know that parallel_cpus must be true. */
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parallel_cpus = false;
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cpu_exec_step(cpu);
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parallel_cpus = true;
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end_exclusive();
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}
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struct tb_desc {
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target_ulong pc;
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target_ulong cs_base;
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2
cpus.c
2
cpus.c
@ -1497,6 +1497,8 @@ static void tcg_exec_all(void)
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if (r == EXCP_DEBUG) {
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cpu_handle_guest_debug(cpu);
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break;
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} else if (r == EXCP_ATOMIC) {
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cpu_exec_step_atomic(cpu);
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}
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} else if (cpu->stop || cpu->stopped) {
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if (cpu->unplug) {
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@ -31,6 +31,7 @@
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#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
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#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
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#define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
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#define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
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/* some important defines:
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*
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@ -59,6 +59,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
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void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
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void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
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void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
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#if !defined(CONFIG_USER_ONLY)
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void cpu_reloading_memory_map(void);
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@ -80,6 +80,7 @@ void tcg_exec_init(unsigned long tb_size);
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bool tcg_enabled(void);
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void cpu_exec_init_all(void);
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void cpu_exec_step_atomic(CPUState *cpu);
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/**
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* set_preferred_target_page_bits:
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@ -354,6 +354,9 @@ void cpu_loop(CPUX86State *env)
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}
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}
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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pc = env->segs[R_CS].base + env->eip;
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EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
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@ -851,6 +854,9 @@ void cpu_loop(CPUARMState *env)
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case EXCP_YIELD:
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/* nothing to do here for user-mode, just resume guest code */
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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error:
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EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
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@ -1051,6 +1057,9 @@ void cpu_loop(CPUARMState *env)
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case EXCP_YIELD:
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/* nothing to do here for user-mode, just resume guest code */
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
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abort();
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@ -1142,6 +1151,9 @@ void cpu_loop(CPUUniCore32State *env)
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}
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}
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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goto error;
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}
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@ -1415,6 +1427,9 @@ void cpu_loop (CPUSPARCState *env)
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}
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}
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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printf ("Unhandled trap: 0x%x\n", trapnr);
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cpu_dump_state(cs, stderr, fprintf, 0);
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@ -1954,6 +1969,9 @@ void cpu_loop(CPUPPCState *env)
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr);
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break;
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@ -2649,6 +2667,9 @@ done_syscall:
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}
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}
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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error:
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EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
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@ -2736,6 +2757,9 @@ void cpu_loop(CPUOpenRISCState *env)
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case EXCP_NR:
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qemu_log_mask(CPU_LOG_INT, "\nNR\n");
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
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trapnr);
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@ -2812,6 +2836,9 @@ void cpu_loop(CPUSH4State *env)
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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printf ("Unhandled trap: 0x%x\n", trapnr);
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cpu_dump_state(cs, stderr, fprintf, 0);
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@ -2879,6 +2906,9 @@ void cpu_loop(CPUCRISState *env)
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}
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}
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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printf ("Unhandled trap: 0x%x\n", trapnr);
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cpu_dump_state(cs, stderr, fprintf, 0);
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@ -2995,6 +3025,9 @@ void cpu_loop(CPUMBState *env)
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}
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}
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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printf ("Unhandled trap: 0x%x\n", trapnr);
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cpu_dump_state(cs, stderr, fprintf, 0);
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@ -3098,6 +3131,9 @@ void cpu_loop(CPUM68KState *env)
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}
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}
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
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abort();
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@ -3334,6 +3370,9 @@ void cpu_loop(CPUAlphaState *env)
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case EXCP_INTERRUPT:
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/* Just indicate that signals should be handled asap. */
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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printf ("Unhandled trap: 0x%x\n", trapnr);
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cpu_dump_state(cs, stderr, fprintf, 0);
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@ -3463,6 +3502,9 @@ void cpu_loop(CPUS390XState *env)
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
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cpu_dump_state(cs, stderr, fprintf, 0);
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@ -3717,6 +3759,9 @@ void cpu_loop(CPUTLGState *env)
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case TILEGX_EXCP_REG_UDN_ACCESS:
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gen_sigill_reg(env);
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
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g_assert_not_reached();
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@ -704,6 +704,7 @@ struct TCGContext {
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};
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extern TCGContext tcg_ctx;
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extern bool parallel_cpus;
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static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
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{
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@ -118,6 +118,7 @@ static void *l1_map[V_L1_MAX_SIZE];
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/* code generation context */
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TCGContext tcg_ctx;
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bool parallel_cpus;
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/* translation block context */
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#ifdef CONFIG_USER_ONLY
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