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target/mips: Introduce mxu_translate_init() helper
Extract the MXU register initialization code from mips_tcg_init() as a new mxu_translate_init() helper. Make it public and replace !TARGET_MIPS64 ifdef'ry by the 'TARGET_LONG_BITS == 32' check to elide this code at preprocessing time. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-13-f4bug@amsat.org>
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@ -2045,7 +2045,20 @@ static const char * const mxuregnames[] = {
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"XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8",
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"XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR",
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};
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#endif
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void mxu_translate_init(void)
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{
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for (unsigned i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
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mxu_gpr[i] = tcg_global_mem_new(cpu_env,
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offsetof(CPUMIPSState, active_tc.mxu_gpr[i]),
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mxuregnames[i]);
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}
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mxu_CR = tcg_global_mem_new(cpu_env,
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offsetof(CPUMIPSState, active_tc.mxu_cr),
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mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
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}
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#endif /* !TARGET_MIPS64 */
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/* General purpose registers moves. */
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void gen_load_gpr(TCGv t, int reg)
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@ -28047,18 +28060,9 @@ void mips_tcg_init(void)
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cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval),
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"llval");
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#if !defined(TARGET_MIPS64)
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for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
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mxu_gpr[i] = tcg_global_mem_new(cpu_env,
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offsetof(CPUMIPSState,
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active_tc.mxu_gpr[i]),
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mxuregnames[i]);
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if (TARGET_LONG_BITS == 32) {
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mxu_translate_init();
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}
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mxu_CR = tcg_global_mem_new(cpu_env,
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offsetof(CPUMIPSState, active_tc.mxu_cr),
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mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
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#endif /* !TARGET_MIPS64 */
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}
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void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb,
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@ -179,6 +179,7 @@ extern TCGv bcond;
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void msa_translate_init(void);
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/* MXU */
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void mxu_translate_init(void);
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bool decode_ase_mxu(DisasContext *ctx, uint32_t insn);
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/* decodetree generated */
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