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62 Commits

Author SHA1 Message Date
malc
606257c6f2 tcg/ppc: Remove redundant comparison from brcond2 
Signed-off-by: malc <av1474@comtv.ru>
 2010-04-18 08:46:29 +04:00
malc
efe72c8de7 tcg/ppc: Fix signed versions of brcond2 
Thanks to: Alexander Graff, Thomas Gleixner and Andreas Faerber.

Signed-off-by: malc <av1474@comtv.ru>
 2010-04-17 08:00:32 +04:00
malc
f7e2aca834 tcg/ppc: Fix typo 
Signed-off-by: malc <av1474@comtv.ru>
 2010-04-06 03:10:03 +04:00
malc
a884dcb804 tcg/ppc: Implment bswap16/32 
Signed-off-by: malc <av1474@comtv.ru>
 2010-04-06 02:54:22 +04:00
malc
aa77bebd98 tcg/ppc: Implement eqv, nand and nor 
Signed-off-by: malc <av1474@comtv.ru>
 2010-04-05 16:09:05 +04:00
Paul Brook
355b194369 Split TLB addend and target_phys_addr_t 
Historically the qemu tlb "addend" field was used for both RAM and IO accesses,
so needed to be able to hold both host addresses (unsigned long) and guest
physical addresses (target_phys_addr_t).  However since the introduction of
the iotlb field it has only been used for RAM accesses.

This means we can change the type of addend to unsigned long, and remove
associated hacks in the big-endian TCG backends.

We can also remove the host dependence from target_phys_addr_t.

Signed-off-by: Paul Brook <paul@codesourcery.com>
 2010-04-05 00:28:53 +01:00
malc
36368cf0d5 tcg/ppc: Fix not_i32 
Thanks to Alexander Graf for bug report and a good reproducible test
case.

Signed-off-by: malc <av1474@comtv.ru>
 2010-04-04 20:36:29 +04:00
Richard Henderson
86feb1c860 tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs. 
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands
sign-extended in 64-bit registers (regardless of the "real" sign
of the operand).  For that, we need to be able to distinguish
between a 32-bit load with a 32-bit result and a 32-bit load with
a given extension to a 64-bit result.  This distinction already
exists for the ld* loads, but not the qemu_ld* loads.

Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for
32-bit outputs.  Adjust all code generators to match.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2010-03-26 23:01:03 +01:00
Richard Henderson
32d98fbd10 tcg: Allow target-specific implementation of NOR. 
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2010-03-26 21:52:44 +01:00
Richard Henderson
9940a96bc8 tcg: Allow target-specific implementation of NAND. 
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2010-03-26 21:44:40 +01:00
Richard Henderson
8d625cf1d1 tcg: Allow target-specific implementation of EQV. 
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2010-03-26 21:42:46 +01:00
Richard Henderson
8a56e84091 tcg: Use TCGCond where appropriate. 
Use the TCGCond enumeration type in the brcond and setcond
related prototypes in tcg-op.h and each code generator.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2010-03-26 21:29:08 +01:00
Richard Henderson
a975160954 tcg: Name the opcode enumeration. 
Give the enumeration formed from tcg-opc.h a name: TCGOpcode.
Use that enumeration type instead of "int" whereever appropriate.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2010-03-26 21:28:24 +01:00
Paolo Bonzini
a63b5829af remove remaining occurrences AREG[1-9] and TCG_AREG[1-9] 
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2010-03-26 20:48:30 +01:00
malc
35f6b5997a tcg/ppc[64]: Only define addend load helpers in softmmu case 
Signed-off-by: malc <av1474@comtv.ru>
 2010-03-13 00:27:46 +03:00
malc
d616cf1d15 tcg/ppc: Fix right rotation 
Signed-off-by: malc <av1474@comtv.ru>
 2010-02-27 02:00:00 +03:00
malc
98b8d951dc tcg/ppc: Fix typo 
Signed-off-by: malc <av1474@comtv.ru>
 2010-02-23 00:50:03 +03:00
malc
65fe043eb4 tcg/ppc: Implement some of the optional ops 
Signed-off-by: malc <av1474@comtv.ru>
 2010-02-22 21:50:01 +03:00
Jay Foad
30c0c76ce0 tcg: fix build on 32-bit hppa, ppc and sparc hosts 
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.

Signed-off-by: Jay Foad <jay.foad@gmail.com>
Signed-off-by: malc <av1474@comtv.ru>
 2010-02-22 19:38:52 +03:00
Richard Henderson
3682825669 tcg: Add comments for all optional instructions not implemented. 
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2010-02-20 08:35:12 +00:00
malc
6ec8523603 tcg/ppc: Consistently use calling convention selection macros 
Signed-off-by: malc <av1474@comtv.ru>
 2010-02-20 01:47:35 +03:00
Juergen Lock
5da79c86a3 Use ppc host calling convention definitions to set TCG_TARGET_CALL_{ALIGN_ARGS,STACK_OFFSET}. 
New version after malc's comments.  (This avoids having to do
  #if defined __linux__ || defined __FreeBSD__ || defined __FreeBSD_kernel__
for the third case.)

Submitted by: Andreas Tobler <andreast@fgznet.ch>  (original version)

Signed-off-by: Juergen Lock <nox@jelal.kn-bremen.de>
Signed-off-by: malc <av1474@comtv.ru>
 2010-02-20 01:37:33 +03:00
malc
27a7797b09 tcg/ppc32: proper setcond implementation 
Signed-off-by: malc <av1474@comtv.ru>
 2010-02-07 02:48:48 +03:00
malc
b0809bf7ca tcg/ppc32: implement setcond[2] 
Signed-off-by: malc <av1474@comtv.ru>
 2010-02-07 02:18:06 +03:00
malc
d937032764 tcg/ppc: always use tcg_out_call 
Signed-off-by: malc <av1474@comtv.ru>
 2009-09-27 14:41:14 +04:00
malc
c45851c44a When targeting PPU use rlwinm instead of andi. if possible 
andi. is microcoded and slow there.

Signed-off-by: malc <av1474@comtv.ru>
 2009-09-06 07:24:37 +04:00
malc
a71836de38 Fix rbase initialization 
Signed-off-by: malc <av1474@comtv.ru>
 2009-07-20 01:15:23 +04:00
malc
f6548c0a4b PPC 32/64 GUEST_BASE support 
Signed-off-by: malc <av1474@comtv.ru>
 2009-07-18 13:16:36 +04:00
malc
4f4a67ae78 Fix LHZX opcode value 
Signed-off-by: malc <av1474@comtv.ru>
 2009-07-18 13:16:13 +04:00
malc
9de187a099 Whack [LS]MW 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-11 07:39:04 +00:00
malc
e23f2f36b1 Remove reserved registers from tcg_target_reg_alloc_order 
Noticed by Andreas Faerber

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7080 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-11 07:38:56 +00:00
blueswir1
e63d7abdde Prune unused TCG_AREGs 
Remove definitions for TCG_AREGs corresponding to AREG definitions
removed in r6778.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-08 14:45:45 +00:00
malc
eb2eb1dc00 Add missing r24..r26 to calle save registers 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6612 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-02-11 18:51:19 +00:00
malc
5db3ee7991 R13 is reserved for small data area pointer by SVR4 PPC ABI 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6450 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-26 18:21:53 +00:00
malc
b1503cda1e Use the ARRAY_SIZE() macro where appropriate. 
Change from v1:
  Avoid changing the existing coding style in certain files.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-22 20:33:55 +00:00
malc
902b3d5c39 Introduce and use cache-utils.[ch] 
Thanks to Segher Boessenkool and Holis Blanchard.

AIX and Darwin cache inquiry:
http://gcc.gnu.org/ml/gcc-patches/2007-08/msg00388.html

Auxiliary vectors:
http://manugarg.googlepages.com/aboutelfauxiliaryvectors

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5973 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-10 19:18:40 +00:00
malc
b29fe3ed48 Preliminary AIX support 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5732 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-18 01:42:22 +00:00
malc
2946898b48 Rename misnamed BACK_CHAIN_OFFSET to LR_OFFSET 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5711 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-12 20:36:24 +00:00
blueswir1
d4a9eb1fc6 Add some missing static and const qualifiers, reg_names only used if NDEBUG set 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-05 09:59:14 +00:00
malc
f8edcbaa2d Avoid clobbering input register in qemu_ld64+bswap+useronly case 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5287 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-22 01:08:08 +00:00
blueswir1
79383c9c08 Fix some warnings that would be generated by gcc -Wredundant-decls 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-30 09:51:20 +00:00
malc
70fa887c14 Relax qemu_ld/st constraints for !SOFTMMU case 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5038 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-21 01:14:07 +00:00
malc
bf6bca527c Account for MacOS X ABI reserved space in linkage area (Andreas Faerber) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4985 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-03 19:04:11 +00:00
malc
f9bf298717 Preliminary MacOS X on PPC32 support 
Big thanks to BlueSwirl for Sparc failure analysis.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4984 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-03 19:04:07 +00:00
malc
52781543ad On ppc32 make tb_set_jmp_target1 behave like it does on a ppc64 
Avoids nasty warnings about flush_icache_range from gcc4 and inability
to compile [cpu-]exec.c with gcc3 and -O, also the function is much
too large to be candidate for inlining anyway.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4974 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-29 20:08:17 +00:00
malc
000a2d866a Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does it 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4961 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-28 23:46:03 +00:00
malc
e46b9681e5 Provide extNs_M instructions 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4934 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-23 20:01:23 +00:00
malc
e924c48573 Fuse EQ and NE handling in tcg_out_brcond2 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4845 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-03 23:49:14 +00:00
malc
8c5e95d807 Mask LL portion of B to 24 bits in tcg_out_b (Thanks to Thiemo Seufer) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4841 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-03 18:51:23 +00:00
malc
ca88500f43 According to gcc-4.3.0/gcc/config/rs6000/crtsavres.asm R13 is volatile 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4779 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-23 05:47:06 +00:00