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We are shortly going to have a split rw/rx jit buffer. Depending on the host, we need to flush the dcache at the rw data pointer and flush the icache at the rx code pointer. For now, the two passed pointers are identical, so there is no effective change in behaviour. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
36 lines
836 B
C
36 lines
836 B
C
/*
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* Flush the host cpu caches.
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef QEMU_CACHEFLUSH_H
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#define QEMU_CACHEFLUSH_H
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/**
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* flush_idcache_range:
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* @rx: instruction address
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* @rw: data address
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* @len: length to flush
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*
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* Flush @len bytes of the data cache at @rw and the icache at @rx
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* to bring them in sync. The two addresses may be different virtual
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* mappings of the same physical page(s).
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*/
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#if defined(__i386__) || defined(__x86_64__) || defined(__s390__)
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static inline void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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{
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/* icache is coherent and does not require flushing. */
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}
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#else
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void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len);
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#endif
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#endif /* QEMU_CACHEFLUSH_H */
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