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f21b36a022
Extra word 2 is stored during tcg compile and `decode_save_opc` needs additional argument in order to pass the value. This will be used during unwind to get extra information about instruction like how to massage exceptions. Updated all callsites as well. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/594 Signed-off-by: Deepak Gupta <debug@rivosinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241008225010.1861630-16-debug@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
135 lines
3.9 KiB
C++
135 lines
3.9 KiB
C++
/*
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* RISC-V translation routines for the RISC-V privileged instructions.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
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{
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/* always generates U-level ECALL, fixed in do_interrupt handler */
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generate_exception(ctx, RISCV_EXCP_U_ECALL);
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return true;
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}
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static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
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{
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target_ulong ebreak_addr = ctx->base.pc_next;
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target_ulong pre_addr = ebreak_addr - 4;
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target_ulong post_addr = ebreak_addr + 4;
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uint32_t pre = 0;
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uint32_t ebreak = 0;
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uint32_t post = 0;
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/*
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* The RISC-V semihosting spec specifies the following
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* three-instruction sequence to flag a semihosting call:
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*
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* slli zero, zero, 0x1f 0x01f01013
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* ebreak 0x00100073
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* srai zero, zero, 0x7 0x40705013
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*
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* The two shift operations on the zero register are no-ops, used
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* here to signify a semihosting exception, rather than a breakpoint.
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*
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* Uncompressed instructions are required so that the sequence is easy
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* to validate.
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*
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* The three instructions are required to lie in the same page so
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* that no exception will be raised when fetching them.
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*/
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if (semihosting_enabled(ctx->priv == PRV_U) &&
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(pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) {
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pre = opcode_at(&ctx->base, pre_addr);
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ebreak = opcode_at(&ctx->base, ebreak_addr);
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post = opcode_at(&ctx->base, post_addr);
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}
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if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
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generate_exception(ctx, RISCV_EXCP_SEMIHOST);
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} else {
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tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
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offsetof(CPURISCVState, badaddr));
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generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
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}
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return true;
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}
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static bool trans_uret(DisasContext *ctx, arg_uret *a)
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{
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return false;
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}
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static bool trans_sret(DisasContext *ctx, arg_sret *a)
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{
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#ifndef CONFIG_USER_ONLY
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if (has_ext(ctx, RVS)) {
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decode_save_opc(ctx, 0);
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translator_io_start(&ctx->base);
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gen_helper_sret(cpu_pc, tcg_env);
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exit_tb(ctx); /* no chaining */
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ctx->base.is_jmp = DISAS_NORETURN;
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} else {
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return false;
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}
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return true;
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#else
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return false;
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#endif
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}
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static bool trans_mret(DisasContext *ctx, arg_mret *a)
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{
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#ifndef CONFIG_USER_ONLY
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decode_save_opc(ctx, 0);
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translator_io_start(&ctx->base);
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gen_helper_mret(cpu_pc, tcg_env);
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exit_tb(ctx); /* no chaining */
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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#else
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return false;
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#endif
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}
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static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
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{
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#ifndef CONFIG_USER_ONLY
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decode_save_opc(ctx, 0);
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gen_update_pc(ctx, ctx->cur_insn_len);
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gen_helper_wfi(tcg_env);
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return true;
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#else
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return false;
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#endif
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}
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static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
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{
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#ifndef CONFIG_USER_ONLY
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decode_save_opc(ctx, 0);
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gen_helper_tlb_flush(tcg_env);
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return true;
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#endif
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return false;
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}
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static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
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{
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return false;
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}
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