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0085bd5161
Define "M" constraint for and_mask_p and "O" constraint for or_mask_p. Assume that inputs are correct in tcg_out_ori and tcg_out_andi. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
118 lines
3.2 KiB
C
118 lines
3.2 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#define TCG_TARGET_HPPA 1
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#if defined(_PA_RISC1_1)
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#define TCG_TARGET_REG_BITS 32
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#else
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#error unsupported
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#endif
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#define TCG_TARGET_WORDS_BIGENDIAN
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#define TCG_TARGET_NB_REGS 32
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enum {
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TCG_REG_R0 = 0,
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TCG_REG_R1,
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TCG_REG_RP,
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TCG_REG_R3,
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TCG_REG_R4,
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TCG_REG_R5,
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TCG_REG_R6,
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TCG_REG_R7,
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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TCG_REG_R11,
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TCG_REG_R12,
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TCG_REG_R13,
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TCG_REG_R14,
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TCG_REG_R15,
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TCG_REG_R16,
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TCG_REG_R17,
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TCG_REG_R18,
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TCG_REG_R19,
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TCG_REG_R20,
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TCG_REG_R21,
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TCG_REG_R22,
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TCG_REG_R23,
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TCG_REG_R24,
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TCG_REG_R25,
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TCG_REG_R26,
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TCG_REG_DP,
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TCG_REG_RET0,
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TCG_REG_RET1,
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TCG_REG_SP,
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TCG_REG_R31,
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};
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#define TCG_CT_CONST_0 0x0100
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#define TCG_CT_CONST_S5 0x0200
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#define TCG_CT_CONST_S11 0x0400
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#define TCG_CT_CONST_MS11 0x0800
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#define TCG_CT_CONST_AND 0x1000
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#define TCG_CT_CONST_OR 0x2000
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_SP
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#define TCG_TARGET_STACK_ALIGN 64
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#define TCG_TARGET_CALL_STACK_OFFSET -48
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#define TCG_TARGET_STATIC_CALL_ARGS_SIZE 8*4
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#define TCG_TARGET_CALL_ALIGN_ARGS 1
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#define TCG_TARGET_STACK_GROWSUP
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/* optional instructions */
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// #define TCG_TARGET_HAS_div_i32
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#define TCG_TARGET_HAS_rot_i32
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#define TCG_TARGET_HAS_ext8s_i32
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#define TCG_TARGET_HAS_ext16s_i32
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#define TCG_TARGET_HAS_ext8u_i32
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#define TCG_TARGET_HAS_ext16u_i32
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#define TCG_TARGET_HAS_bswap16_i32
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#define TCG_TARGET_HAS_bswap32_i32
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#define TCG_TARGET_HAS_not_i32
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#define TCG_TARGET_HAS_neg_i32
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#define TCG_TARGET_HAS_andc_i32
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// #define TCG_TARGET_HAS_orc_i32
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#define TCG_TARGET_HAS_GUEST_BASE
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/* Note: must be synced with dyngen-exec.h */
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#define TCG_AREG0 TCG_REG_R17
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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start &= ~31;
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while (start <= stop) {
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asm volatile ("fdc 0(%0)\n\t"
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"sync\n\t"
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"fic 0(%%sr4, %0)\n\t"
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"sync"
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: : "r"(start) : "memory");
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start += 32;
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}
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}
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