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ee45203646
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023121821.19179-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
147 lines
3.4 KiB
C
147 lines
3.4 KiB
C
/*
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* MicroBlaze gdb server stub
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/gdbstub.h"
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/*
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* GDB expects SREGs in the following order:
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* PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI.
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*
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* PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't
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* map them to anything and return a value of 0 instead.
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*/
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enum {
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GDB_PC = 32 + 0,
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GDB_MSR = 32 + 1,
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GDB_EAR = 32 + 2,
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GDB_ESR = 32 + 3,
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GDB_FSR = 32 + 4,
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GDB_BTR = 32 + 5,
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GDB_PVR0 = 32 + 6,
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GDB_PVR11 = 32 + 17,
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GDB_EDR = 32 + 18,
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GDB_SLR = 32 + 25,
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GDB_SHR = 32 + 26,
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};
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int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUClass *cc = CPU_GET_CLASS(cs);
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CPUMBState *env = &cpu->env;
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uint32_t val;
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if (n > cc->gdb_num_core_regs) {
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return 0;
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}
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switch (n) {
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case 1 ... 31:
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val = env->regs[n];
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break;
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case GDB_PC:
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val = env->pc;
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break;
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case GDB_MSR:
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val = mb_cpu_read_msr(env);
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break;
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case GDB_EAR:
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val = env->ear;
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break;
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case GDB_ESR:
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val = env->esr;
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break;
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case GDB_FSR:
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val = env->fsr;
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break;
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case GDB_BTR:
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val = env->btr;
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break;
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case GDB_PVR0 ... GDB_PVR11:
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/* PVR12 is intentionally skipped */
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val = cpu->cfg.pvr_regs[n - GDB_PVR0];
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break;
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case GDB_EDR:
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val = env->edr;
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break;
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case GDB_SLR:
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val = env->slr;
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break;
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case GDB_SHR:
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val = env->shr;
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break;
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default:
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/* Other SRegs aren't modeled, so report a value of 0 */
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val = 0;
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break;
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}
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return gdb_get_reg32(mem_buf, val);
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}
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int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUClass *cc = CPU_GET_CLASS(cs);
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CPUMBState *env = &cpu->env;
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uint32_t tmp;
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if (n > cc->gdb_num_core_regs) {
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return 0;
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}
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tmp = ldl_p(mem_buf);
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switch (n) {
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case 1 ... 31:
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env->regs[n] = tmp;
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break;
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case GDB_PC:
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env->pc = tmp;
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break;
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case GDB_MSR:
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mb_cpu_write_msr(env, tmp);
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break;
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case GDB_EAR:
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env->ear = tmp;
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break;
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case GDB_ESR:
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env->esr = tmp;
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break;
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case GDB_FSR:
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env->fsr = tmp;
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break;
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case GDB_BTR:
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env->btr = tmp;
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break;
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case GDB_EDR:
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env->edr = tmp;
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break;
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case GDB_SLR:
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env->slr = tmp;
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break;
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case GDB_SHR:
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env->shr = tmp;
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break;
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}
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return 4;
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}
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