xemu/target/openrisc
Claudio Fontana 7827168471 cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
we cannot in principle make the TCG Operations field definitions
conditional on CONFIG_TCG in code that is included by both common_ss
and specific_ss modules.

Therefore, what we can do safely to restrict the TCG fields to TCG-only
builds, is to move all tcg cpu operations into a separate header file,
which is only included by TCG, target-specific code.

This leaves just a NULL pointer in the cpu.h for the non-TCG builds.

This also tidies up the code in all targets a bit, having all TCG cpu
operations neatly contained by a dedicated data struct.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210204163931.7358-16-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05 10:24:15 -10:00
..
cpu-param.h
cpu.c cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass 2021-02-05 10:24:15 -10:00
cpu.h target/openrisc: Move pic_cpu code into CPU object proper 2020-12-15 12:04:30 +00:00
disas.c meson: target 2020-08-21 06:30:35 -04:00
exception_helper.c
exception.c
exception.h Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
fpu_helper.c softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
gdbstub.c gdbstub: extend GByteArray to read register helpers 2020-03-17 17:38:38 +00:00
helper.h target/openrisc: Implement unordered fp comparisons 2019-09-04 12:57:59 -07:00
insns.decode target/openrisc: Implement l.adrp 2019-09-04 12:59:00 -07:00
interrupt_helper.c
interrupt.c Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
machine.c migration: Replace migration's JSON writer by the general one 2020-12-19 10:39:16 +01:00
meson.build meson: target 2020-08-21 06:30:35 -04:00
mmu.c Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
sys_helper.c target/openrisc: Remove dead code attempting to check "is timer disabled" 2020-11-17 12:56:32 +00:00
translate.c meson: target 2020-08-21 06:30:35 -04:00