xemu/target
Emilio G. Cota 068a5ea02f qom: convert the CPU list to RCU
Iterating over the list without using atomics is undefined behaviour,
since the list can be modified concurrently by other threads (e.g.
every time a new thread is created in user-mode).

Fix it by implementing the CPU list as an RCU QTAILQ. This requires
a little bit of extra work to traverse list in reverse order (see
previous patch), but other than that the conversion is trivial.

Signed-off-by: Emilio G. Cota <cota@braap.org>
Message-Id: <20180819091335.22863-12-cota@braap.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-08-23 18:46:25 +02:00
..
alpha tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
arm fix "Missing break in switch" coverity reports 2018-08-23 13:32:50 +02:00
cris tcg-next queue 2018-06-04 11:28:31 +01:00
hppa tcg-next queue 2018-06-04 11:28:31 +01:00
i386 target-i386: fix segment limit check in ljmp 2018-08-23 18:46:25 +02:00
lm32 tcg-next queue 2018-06-04 11:28:31 +01:00
m68k target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn 2018-06-11 12:43:42 +02:00
microblaze target-microblaze: Rework NOP/zero instruction handling 2018-06-15 09:05:00 +02:00
mips target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 2018-08-16 19:18:45 +02:00
moxie tcg-next queue 2018-06-04 11:28:31 +01:00
nios2 tcg-next queue 2018-06-04 11:28:31 +01:00
openrisc target/openrisc: Fix writes to interrupt mask register 2018-07-03 22:40:33 +09:00
ppc target/ppc: fix build on ppc64 host 2018-07-07 12:12:27 +10:00
riscv RISC-V: Add trailing '\n' to qemu_log() calls 2018-06-08 13:15:33 +01:00
s390x qom: convert the CPU list to RCU 2018-08-23 18:46:25 +02:00
sh4 sh4: fix use_icount with linux-user 2018-08-20 00:11:06 +02:00
sparc SPARC64: add icount support 2018-06-17 11:13:06 +01:00
tilegx tcg-next queue 2018-06-04 11:28:31 +01:00
tricore tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
unicore32 tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
xtensa target/xtensa/cpu: Set owner of memory region in xtensa_cpu_initfn 2018-08-06 19:07:21 +01:00