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71b7f54fdf
* remove pointless 'info pcmcia' and a lot of now-dead code * register ARM cpu reset handlers even if not using -kernel * update to libvixl 1.6 * various minor code cleanups * support PSCI under TCG ('virt' machine can now be shut down, SMP configurations work) * correct the sense of the AArch64 DCZID DZP bit * report a valid L1Ip field in CTR_EL0 for CPU type "any" * correctly UNDEF writes to FPINST/FPINST2 from EL0 * more preparatory code refactoring for EL2/EL3 support -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJUSjmYAAoJEDwlJe0UNgzebJgQAJnPbPNhwT/S4xbE+RVpJDPY tkmFOwMijao7w1+teg2HmG5QwGDe/Fyzr15Abp5Kx7DxhdN2qflWCgZYnmxaQfJe e2MRpvmyji8nrHEhBqvdEj/qA0j0BuO//QaDU2JDeyM0CZ3un6kzHArLNMiV5nSj DXhl9/Zn6zuvUOEi605zFc5mVchMzen6Mvc4bHNUWgE/eGH1/o/UyUjQRhaCyAwI owDbKohKFWQ9wpsUQVGeH3inTFNDMcFNggDnuw9F+GowUXK7usQhulHoix8Wfhi9 ku47kp1w7XrF0sp05dCjh9pK9F0iv0gbdh5Wg31yaw7pCEWwLiPWHblu2BoGc37P pEqI/H21eImGfnLT04EPO0w1KD5B3OapSqI8Tsq9l3hd2yXtHm8KVk2eEGfUJpuN pAePNEwhYX2oqHugrH1zkZXEsSw7VsY57WOCkmwwLdKf6xdbqJwdWEehxLUdkiSx KcYYkO8g6voDUBUvhpDrlmSceUgzFqCE7wrcwhOiQQ5oY8jDd5DE5Gtg1I/T7yXc 5wXeNh6nSj/MYtL4sYBiEEOVI/aaDiK6xqUxeT38VhI5amCj2EARfLEb2qqo25aC mmB6WujUFQmu3Eu95lK5Iced3ZjbjcJ8UaSu3NwSTiAATqf8ezTSdSktLDNmpPpj jsgOKj9aDOBP9aWNaGlp =uBin -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20141024' into staging target-arm queue: * remove pointless 'info pcmcia' and a lot of now-dead code * register ARM cpu reset handlers even if not using -kernel * update to libvixl 1.6 * various minor code cleanups * support PSCI under TCG ('virt' machine can now be shut down, SMP configurations work) * correct the sense of the AArch64 DCZID DZP bit * report a valid L1Ip field in CTR_EL0 for CPU type "any" * correctly UNDEF writes to FPINST/FPINST2 from EL0 * more preparatory code refactoring for EL2/EL3 support # gpg: Signature made Fri 24 Oct 2014 12:35:52 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20141024: (23 commits) target-arm: A32: Emulate the SMC instruction target-arm: make arm_current_el() return EL3 target-arm: rename arm_current_pl to arm_current_el target-arm: reject switching to monitor mode target-arm: add arm_is_secure() function target-arm: increase arrays of registers R13 & R14 target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0 target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any" target-arm: Correct sense of the DCZID DZP bit arm/virt: enable PSCI emulation support for system emulation target-arm: add emulation of PSCI calls for system emulation target-arm: Add support for A32 and T32 HVC and SMC insns target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers target-arm: add missing PSCI constants needed for PSCI emulation target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes target-arm: add powered off cpu state omap_gpmc.c: Remove duplicate assignment disas/libvixl/a64/instructions-a64.h: Remove unused constants arm_gic: remove unused parameter. disas/libvixl: Update to libvixl 1.6 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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fpu | ||
hw | ||
libdecnumber | ||
migration | ||
monitor | ||
net | ||
qapi | ||
qemu | ||
qom | ||
sysemu | ||
ui | ||
config.h | ||
elf.h | ||
glib-compat.h | ||
qemu-common.h | ||
qemu-io.h | ||
trace-tcg.h | ||
trace.h |