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d6bafaf45c
Now that the Xilinx CSU DMA model is implemented, the existing DMA related dead codes in the ZynqMP QSPI are useless and should be removed. The maximum register number is also updated to only include the QSPI registers. Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210303135254.3970-6-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
144 lines
3.8 KiB
C
144 lines
3.8 KiB
C
/*
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* Header file for the Xilinx Zynq SPI controller
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*
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* Copyright (C) 2015 Xilinx Inc
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef XILINX_SPIPS_H
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#define XILINX_SPIPS_H
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#include "hw/ssi/ssi.h"
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#include "qemu/fifo32.h"
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#include "hw/stream.h"
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#include "hw/sysbus.h"
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#include "qom/object.h"
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typedef struct XilinxSPIPS XilinxSPIPS;
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#define XLNX_SPIPS_R_MAX (0x100 / 4)
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#define XLNX_ZYNQMP_SPIPS_R_MAX (0x200 / 4)
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/* Bite off 4k chunks at a time */
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#define LQSPI_CACHE_SIZE 1024
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#define QSPI_DMA_MAX_BURST_SIZE 2048
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typedef enum {
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READ = 0x3, READ_4 = 0x13,
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FAST_READ = 0xb, FAST_READ_4 = 0x0c,
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DOR = 0x3b, DOR_4 = 0x3c,
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QOR = 0x6b, QOR_4 = 0x6c,
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DIOR = 0xbb, DIOR_4 = 0xbc,
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QIOR = 0xeb, QIOR_4 = 0xec,
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PP = 0x2, PP_4 = 0x12,
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DPP = 0xa2,
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QPP = 0x32, QPP_4 = 0x34,
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} FlashCMD;
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struct XilinxSPIPS {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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MemoryRegion mmlqspi;
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qemu_irq irq;
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int irqline;
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uint8_t num_cs;
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uint8_t num_busses;
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uint8_t snoop_state;
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int cmd_dummies;
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uint8_t link_state;
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uint8_t link_state_next;
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uint8_t link_state_next_when;
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qemu_irq *cs_lines;
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bool *cs_lines_state;
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SSIBus **spi;
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Fifo8 rx_fifo;
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Fifo8 tx_fifo;
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uint8_t num_txrx_bytes;
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uint32_t rx_discard;
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uint32_t regs[XLNX_SPIPS_R_MAX];
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bool man_start_com;
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};
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struct XilinxQSPIPS {
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XilinxSPIPS parent_obj;
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uint8_t lqspi_buf[LQSPI_CACHE_SIZE];
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hwaddr lqspi_cached_addr;
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Error *migration_blocker;
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bool mmio_execution_enabled;
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};
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typedef struct XilinxQSPIPS XilinxQSPIPS;
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struct XlnxZynqMPQSPIPS {
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XilinxQSPIPS parent_obj;
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StreamSink *dma;
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int gqspi_irqline;
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uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX];
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/* GQSPI has seperate tx/rx fifos */
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Fifo8 rx_fifo_g;
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Fifo8 tx_fifo_g;
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Fifo32 fifo_g;
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/*
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* At the end of each generic command, misaligned extra bytes are discard
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* or padded to tx and rx respectively to round it out (and avoid need for
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* individual byte access. Since we use byte fifos, keep track of the
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* alignment WRT to word access.
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*/
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uint8_t rx_fifo_g_align;
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uint8_t tx_fifo_g_align;
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bool man_start_com_g;
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uint32_t dma_burst_size;
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uint8_t dma_buf[QSPI_DMA_MAX_BURST_SIZE];
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};
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struct XilinxSPIPSClass {
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SysBusDeviceClass parent_class;
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const MemoryRegionOps *reg_ops;
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uint32_t rx_fifo_size;
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uint32_t tx_fifo_size;
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};
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#define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
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#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
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#define TYPE_XLNX_ZYNQMP_QSPIPS "xlnx.usmp-gqspi"
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OBJECT_DECLARE_TYPE(XilinxSPIPS, XilinxSPIPSClass, XILINX_SPIPS)
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OBJECT_DECLARE_SIMPLE_TYPE(XilinxQSPIPS, XILINX_QSPIPS)
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPQSPIPS, XLNX_ZYNQMP_QSPIPS)
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#endif /* XILINX_SPIPS_H */
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