Bin Meng 11ec06f9ea hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id ...

Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.

Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211020014112.7336-7-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2021-10-22 23:35:47 +10:00

..

boot.c

target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl

2021-10-22 07:47:51 +10:00

Kconfig

hw/intc: Rename sifive_clint sources to riscv_aclint sources

2021-09-21 07:56:49 +10:00

meson.build

hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines

2021-07-20 15:32:49 +02:00

microchip_pfsoc.c

hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id

2021-10-22 23:35:47 +10:00

numa.c

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00

opentitan.c

hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id

2021-10-22 23:35:47 +10:00

riscv_hart.c

hw/riscv: hart: Add a new 'resetvec' property

2020-09-09 15:54:18 -07:00

shakti_c.c

hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id

2021-10-22 23:35:47 +10:00

sifive_e.c

hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id

2021-10-22 23:35:47 +10:00

sifive_u.c

hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id

2021-10-22 23:35:47 +10:00

spike.c

hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id

2021-10-22 23:35:47 +10:00

virt.c

hw/riscv: virt: Use machine->ram as the system memory

2021-10-22 07:47:51 +10:00