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fcf5ef2ab5
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
91 lines
2.9 KiB
C
91 lines
2.9 KiB
C
/*
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* Microblaze MMU emulation for qemu.
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*
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* Copyright (c) 2009 Edgar E. Iglesias
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#define MMU_R_PID 0
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#define MMU_R_ZPR 1
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#define MMU_R_TLBX 2
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#define MMU_R_TLBLO 3
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#define MMU_R_TLBHI 4
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#define MMU_R_TLBSX 5
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#define RAM_DATA 1
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#define RAM_TAG 0
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/* Tag portion */
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#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */
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#define TLB_PAGESZ_MASK 0x00000380
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#define TLB_PAGESZ(x) (((x) & 0x7) << 7)
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#define PAGESZ_1K 0
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#define PAGESZ_4K 1
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#define PAGESZ_16K 2
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#define PAGESZ_64K 3
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#define PAGESZ_256K 4
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#define PAGESZ_1M 5
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#define PAGESZ_4M 6
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#define PAGESZ_16M 7
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#define TLB_VALID 0x00000040 /* Entry is valid */
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/* Data portion */
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#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */
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#define TLB_PERM_MASK 0x00000300
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#define TLB_EX 0x00000200 /* Instruction execution allowed */
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#define TLB_WR 0x00000100 /* Writes permitted */
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#define TLB_ZSEL_MASK 0x000000F0
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#define TLB_ZSEL(x) (((x) & 0xF) << 4)
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#define TLB_ATTR_MASK 0x0000000F
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#define TLB_W 0x00000008 /* Caching is write-through */
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#define TLB_I 0x00000004 /* Caching is inhibited */
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#define TLB_M 0x00000002 /* Memory is coherent */
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#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
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#define TLB_ENTRIES 64
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struct microblaze_mmu
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{
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/* Data and tag brams. */
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uint32_t rams[2][TLB_ENTRIES];
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/* We keep a separate ram for the tids to avoid the 48 bit tag width. */
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uint8_t tids[TLB_ENTRIES];
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/* Control flops. */
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uint32_t regs[8];
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int c_mmu;
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int c_mmu_tlb_access;
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int c_mmu_zones;
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};
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struct microblaze_mmu_lookup
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{
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uint32_t paddr;
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uint32_t vaddr;
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unsigned int size;
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unsigned int idx;
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int prot;
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enum {
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ERR_PROT, ERR_MISS, ERR_HIT
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} err;
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};
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unsigned int mmu_translate(struct microblaze_mmu *mmu,
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struct microblaze_mmu_lookup *lu,
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target_ulong vaddr, int rw, int mmu_idx);
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uint32_t mmu_read(CPUMBState *env, uint32_t rn);
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void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v);
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void mmu_init(struct microblaze_mmu *mmu);
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