Alistair Francis 0feb4a7129 riscv: plic: Fix incorrect irq calculation ... This patch fixes four different things, to maintain bisectability they have been merged into a single patch. The following fixes are below: sifive_plic: Fix incorrect irq calculation The irq is incorrectly calculated to be off by one. It has worked in the past as the priority_base offset has also been set incorrectly. We are about to fix the priority_base offset so first first the irq calculation. sifive_u: Fix PLIC priority base offset and numbering According to the FU540 manual the PLIC source priority address starts at an offset of 0x04 and not 0x00. The same manual also specifies that the PLIC only has 53 source priorities. Fix these two incorrect header files. We also need to over extend the plic_gpios[] array as the PLIC sources count from 1 and not 0. riscv: sifive_e: Fix PLIC priority base offset According to the FE31 manual the PLIC source priority address starts at an offset of 0x04 and not 0x00. riscv: virt: Fix PLIC priority base offset Update the virt offsets based on the newly updated SiFive U and SiFive E offsets. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-04-04 16:36:19 -07:00
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riscv_hart.h
riscv_htif.h
sifive_clint.h	RISC-V: Replace hardcoded constants with enum values	2018-05-06 10:39:38 +12:00
sifive_e.h	riscv: plic: Fix incorrect irq calculation	2019-04-04 16:36:19 -07:00
sifive_plic.h	RISC-V: Use atomic_cmpxchg to update PLIC bitmaps	2018-09-04 13:19:31 -07:00
sifive_prci.h	SiFive RISC-V PRCI Block	2018-03-07 08:30:28 +13:00
sifive_test.h	SiFive RISC-V Test Finisher	2018-03-07 08:30:28 +13:00
sifive_u.h	riscv: plic: Fix incorrect irq calculation	2019-04-04 16:36:19 -07:00
sifive_uart.h	sifive_uart: Implement interrupt pending register	2018-12-20 12:08:43 -08:00
spike.h	RISC-V: Make some header guards more specific	2018-05-06 10:39:38 +12:00
virt.h	riscv: plic: Fix incorrect irq calculation	2019-04-04 16:36:19 -07:00