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Per E500 core reference manual [1], chapter 8.4.4 "Branch Taken Debug Event" and chapter 8.4.5 "Instruction Complete Debug Event": "A branch taken debug event occurs if both MSR[DE] and DBCR0[BRT] are set ... Branch taken debug events are not recognized if MSR[DE] is cleared when the branch instruction executes." "An instruction complete debug event occurs when any instruction completes execution so long as MSR[DE] and DBCR0[ICMP] are both set ... Instruction complete debug events are not recognized if MSR[DE] is cleared at the time of the instruction execution." Current codes do not check MSR.DE bit before setting HFLAGS_SE and HFLAGS_BE flag, which would cause the immediate debug interrupt to be generated, e.g.: when DBCR0.ICMP bit is set by guest software and MSR.DE is not set. [1] https://www.nxp.com/docs/en/reference-manual/E500CORERM.pdf Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Lucas Mateus Castro <lucas.araujo@eldorado.org.br> Message-Id: <20220421011729.1148727-1-bmeng.cn@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> |
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