Peter Maydell 126eeee6c7 target-arm queue: ... * xlnx-zdma: Fix endianness handling of descriptor loading * nrf51: Fix last GPIO CNF address * gicv3: Use gicr_typer in arm_gicv3_icc_reset * msf2: Add EMAC block to SmartFusion2 SoC * New clock modelling framework * hw/arm: versal: Setup the ADMA with 128bit bus-width * Cadence: gem: fix wraparound in 64bit descriptors * cadence_gem: clear RX control descriptor * target/arm: Vectorize integer comparison vs zero * hw/arm/virt: dt: add kaslr-seed property * hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAl6q5CoZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pWPD/9zjcV3TlOUWg/2aRQOYWB1 I/h2AGTI09Y/nGMmwvHEyQKyAg6mL8KfJwCUDHr1pE3DeTt4Z7dA+3rhk1uy+gKA Ot/7e4IVSMiNh28xkBiSPviBXjYtgmVjvSlgKn4fty6g+30wdGV8ymNz1wXO8II0 5cuGlaz0VQ4N+W4qz9kuaJNEAsMSnmrJ9fUzZDllRsNy4li3aSR4sQ9CymsJ23+3 9CdStk/ibA7tExDX5qkj4lKozENEAU/jethA91CQCMLnK/7aGfHbLqVyWu6xDuQ7 oTdyXr7nrGIUjod+Cx7mLyUQKXVfsiw0x4kmjvOnaVZHh5oIgDj83vWXQ28nC6P4 wVYCRWpg68GPuaEru8VeocdoATMa1ONjrv5/gFGOxlma4AjD07WQ53hTp2pL0HT2 +uYPwm2iSYgYKX7QV/rbNzWHK1nYq6/3LDeVQc6nr/3jVewpZngnf2pMxChRUUoT qtdLwJL/om9hqV4lsU7cxHKSNnkocfDhjkwRy6wg0L/iXDftt1sKbZO+G78vvsow S+NqjpAo4m+P7ExS8DGiSsgvQIQIHvcjjpeym4fWmBxPaXep6oUIewzBuExcYWK8 XogFZEnW6PNyr/CKLh7GYH9C0F6FI36+yPUZFxvdBpz4w5QBADYKyyG0/53P0uKa ez3ixFfplzcx8RIiy+nIsQ== =9plU -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200430-1' into staging target-arm queue: * xlnx-zdma: Fix endianness handling of descriptor loading * nrf51: Fix last GPIO CNF address * gicv3: Use gicr_typer in arm_gicv3_icc_reset * msf2: Add EMAC block to SmartFusion2 SoC * New clock modelling framework * hw/arm: versal: Setup the ADMA with 128bit bus-width * Cadence: gem: fix wraparound in 64bit descriptors * cadence_gem: clear RX control descriptor * target/arm: Vectorize integer comparison vs zero * hw/arm/virt: dt: add kaslr-seed property * hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes # gpg: Signature made Thu 30 Apr 2020 15:43:54 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200430-1: (30 commits) hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102 device_tree: Constify compat in qemu_fdt_node_path() device_tree: Allow name wildcards in qemu_fdt_node_path() target/arm/cpu: Update coding style to make checkpatch.pl happy target/arm: Make cpu_register() available for other files target/arm: Restrict the Address Translate write operation to TCG accel hw/arm/virt: dt: add kaslr-seed property hw/arm/virt: dt: move creation of /secure-chosen to create_fdt() target/arm: Vectorize integer comparison vs zero net: cadence_gem: clear RX control descriptor Cadence: gem: fix wraparound in 64bit descriptors hw/arm: versal: Setup the ADMA with 128bit bus-width qdev-monitor: print the device's clock with info qtree hw/arm/xilinx_zynq: connect uart clocks to slcr hw/char/cadence_uart: add clock support hw/misc/zynq_slcr: add clock generation for uarts docs/clocks: add device's clock documentation qdev-clock: introduce an init array to ease the device construction qdev: add clock input&output support to devices. ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2020-04-30 15:45:34 +01:00
..
alpha	x86 and machine queue for 5.0 soft freeze	2020-03-19 14:22:46 +00:00
arm	target/arm/cpu: Update coding style to make checkpatch.pl happy	2020-04-30 15:35:41 +01:00
cris	x86 and machine queue for 5.0 soft freeze	2020-03-19 14:22:46 +00:00
hppa	x86 and machine queue for 5.0 soft freeze	2020-03-19 14:22:46 +00:00
i386	various: Remove suspicious '\' character outside of #define in C code	2020-04-29 08:01:51 +02:00
lm32	x86 and machine queue for 5.0 soft freeze	2020-03-19 14:22:46 +00:00
m68k	target/m68k/helper: Fix m68k_fpu_gdb_get_reg() use of GByteArray	2020-04-15 11:38:23 +01:00
microblaze	various: Remove suspicious '\' character outside of #define in C code	2020-04-29 08:01:51 +02:00
mips	target/mips: Fix loongson multimedia condition instructions	2020-03-28 14:09:45 -07:00
moxie	cpu: Use DeviceClass reset instead of a special CPUClass reset	2020-03-17 19:48:10 -04:00
nios2	x86 and machine queue for 5.0 soft freeze	2020-03-19 14:22:46 +00:00
openrisc	x86 and machine queue for 5.0 soft freeze	2020-03-19 14:22:46 +00:00
ppc	various: Remove suspicious '\' character outside of #define in C code	2020-04-29 08:01:51 +02:00
riscv	target/riscv: Add a sifive-e34 cpu type	2020-04-29 13:16:37 -07:00
rx	target/rx/translate: Add missing fall through comment	2020-04-07 18:45:54 -07:00
s390x	s390x: Add unpack facility feature to GA1	2020-04-29 14:31:32 +02:00
sh4	gdbstub: Introduce gdb_get_float32() to get 32-bit float registers	2020-04-15 11:38:23 +01:00
sparc	x86 and machine queue for 5.0 soft freeze	2020-03-19 14:22:46 +00:00
tilegx	cpu: Use DeviceClass reset instead of a special CPUClass reset	2020-03-17 19:48:10 -04:00
tricore	cpu: Use DeviceClass reset instead of a special CPUClass reset	2020-03-17 19:48:10 -04:00
unicore32	tcg: Search includes from the project root source directory	2020-01-15 15:13:10 -10:00
xtensa	gdbstub: Do not use memset() on GByteArray	2020-04-15 11:38:23 +01:00