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6b9409ba5f
After a migration the clock offset is updated, but we also need to re-arm the alarm if needed. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201220112615.933036-7-laurent@vivier.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
299 lines
8.4 KiB
C
299 lines
8.4 KiB
C
/*
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* Goldfish virtual platform RTC
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*
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* Copyright (C) 2019 Western Digital Corporation or its affiliates.
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*
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* For more details on Google Goldfish virtual platform refer:
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* https://android.googlesource.com/platform/external/qemu/+/refs/heads/emu-2.0-release/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "hw/rtc/goldfish_rtc.h"
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#include "migration/vmstate.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "qemu/bitops.h"
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#include "qemu/timer.h"
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#include "sysemu/sysemu.h"
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#include "qemu/cutils.h"
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#include "qemu/log.h"
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#include "trace.h"
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#define RTC_TIME_LOW 0x00
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#define RTC_TIME_HIGH 0x04
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#define RTC_ALARM_LOW 0x08
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#define RTC_ALARM_HIGH 0x0c
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#define RTC_IRQ_ENABLED 0x10
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#define RTC_CLEAR_ALARM 0x14
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#define RTC_ALARM_STATUS 0x18
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#define RTC_CLEAR_INTERRUPT 0x1c
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static void goldfish_rtc_update(GoldfishRTCState *s)
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{
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qemu_set_irq(s->irq, (s->irq_pending & s->irq_enabled) ? 1 : 0);
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}
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static void goldfish_rtc_interrupt(void *opaque)
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{
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GoldfishRTCState *s = (GoldfishRTCState *)opaque;
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s->alarm_running = 0;
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s->irq_pending = 1;
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goldfish_rtc_update(s);
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}
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static uint64_t goldfish_rtc_get_count(GoldfishRTCState *s)
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{
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return s->tick_offset + (uint64_t)qemu_clock_get_ns(rtc_clock);
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}
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static void goldfish_rtc_clear_alarm(GoldfishRTCState *s)
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{
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timer_del(s->timer);
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s->alarm_running = 0;
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}
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static void goldfish_rtc_set_alarm(GoldfishRTCState *s)
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{
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uint64_t ticks = goldfish_rtc_get_count(s);
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uint64_t event = s->alarm_next;
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if (event <= ticks) {
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goldfish_rtc_clear_alarm(s);
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goldfish_rtc_interrupt(s);
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} else {
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/*
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* We should be setting timer expiry to:
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* qemu_clock_get_ns(rtc_clock) + (event - ticks)
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* but this is equivalent to:
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* event - s->tick_offset
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*/
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timer_mod(s->timer, event - s->tick_offset);
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s->alarm_running = 1;
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}
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}
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static uint64_t goldfish_rtc_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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GoldfishRTCState *s = opaque;
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uint64_t r = 0;
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/*
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* From the documentation linked at the top of the file:
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*
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* To read the value, the kernel must perform an IO_READ(TIME_LOW), which
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* returns an unsigned 32-bit value, before an IO_READ(TIME_HIGH), which
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* returns a signed 32-bit value, corresponding to the higher half of the
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* full value.
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*/
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switch (offset) {
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case RTC_TIME_LOW:
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r = goldfish_rtc_get_count(s);
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s->time_high = r >> 32;
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r &= 0xffffffff;
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break;
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case RTC_TIME_HIGH:
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r = s->time_high;
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break;
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case RTC_ALARM_LOW:
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r = s->alarm_next & 0xffffffff;
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break;
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case RTC_ALARM_HIGH:
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r = s->alarm_next >> 32;
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break;
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case RTC_IRQ_ENABLED:
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r = s->irq_enabled;
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break;
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case RTC_ALARM_STATUS:
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r = s->alarm_running;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: offset 0x%x is UNIMP.\n", __func__, (uint32_t)offset);
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break;
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}
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trace_goldfish_rtc_read(offset, r);
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return r;
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}
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static void goldfish_rtc_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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GoldfishRTCState *s = opaque;
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uint64_t current_tick, new_tick;
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switch (offset) {
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case RTC_TIME_LOW:
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current_tick = goldfish_rtc_get_count(s);
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new_tick = deposit64(current_tick, 0, 32, value);
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s->tick_offset += new_tick - current_tick;
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break;
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case RTC_TIME_HIGH:
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current_tick = goldfish_rtc_get_count(s);
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new_tick = deposit64(current_tick, 32, 32, value);
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s->tick_offset += new_tick - current_tick;
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break;
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case RTC_ALARM_LOW:
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s->alarm_next = deposit64(s->alarm_next, 0, 32, value);
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goldfish_rtc_set_alarm(s);
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break;
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case RTC_ALARM_HIGH:
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s->alarm_next = deposit64(s->alarm_next, 32, 32, value);
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break;
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case RTC_IRQ_ENABLED:
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s->irq_enabled = (uint32_t)(value & 0x1);
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goldfish_rtc_update(s);
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break;
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case RTC_CLEAR_ALARM:
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goldfish_rtc_clear_alarm(s);
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break;
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case RTC_CLEAR_INTERRUPT:
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s->irq_pending = 0;
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goldfish_rtc_update(s);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: offset 0x%x is UNIMP.\n", __func__, (uint32_t)offset);
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break;
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}
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trace_goldfish_rtc_write(offset, value);
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}
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static int goldfish_rtc_pre_save(void *opaque)
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{
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uint64_t delta;
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GoldfishRTCState *s = opaque;
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/*
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* We want to migrate this offset, which sounds straightforward.
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* Unfortunately, we cannot directly pass tick_offset because
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* rtc_clock on destination Host might not be same source Host.
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*
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* To tackle, this we pass tick_offset relative to vm_clock from
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* source Host and make it relative to rtc_clock at destination Host.
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*/
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delta = qemu_clock_get_ns(rtc_clock) -
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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s->tick_offset_vmstate = s->tick_offset + delta;
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return 0;
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}
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static int goldfish_rtc_post_load(void *opaque, int version_id)
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{
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uint64_t delta;
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GoldfishRTCState *s = opaque;
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/*
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* We extract tick_offset from tick_offset_vmstate by doing
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* reverse math compared to pre_save() function.
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*/
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delta = qemu_clock_get_ns(rtc_clock) -
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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s->tick_offset = s->tick_offset_vmstate - delta;
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goldfish_rtc_set_alarm(s);
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return 0;
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}
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static const MemoryRegionOps goldfish_rtc_ops = {
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.read = goldfish_rtc_read,
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.write = goldfish_rtc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4
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}
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};
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static const VMStateDescription goldfish_rtc_vmstate = {
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.name = TYPE_GOLDFISH_RTC,
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.version_id = 2,
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.pre_save = goldfish_rtc_pre_save,
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.post_load = goldfish_rtc_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(tick_offset_vmstate, GoldfishRTCState),
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VMSTATE_UINT64(alarm_next, GoldfishRTCState),
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VMSTATE_UINT32(alarm_running, GoldfishRTCState),
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VMSTATE_UINT32(irq_pending, GoldfishRTCState),
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VMSTATE_UINT32(irq_enabled, GoldfishRTCState),
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VMSTATE_UINT32(time_high, GoldfishRTCState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void goldfish_rtc_reset(DeviceState *dev)
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{
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GoldfishRTCState *s = GOLDFISH_RTC(dev);
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struct tm tm;
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timer_del(s->timer);
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qemu_get_timedate(&tm, 0);
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s->tick_offset = mktimegm(&tm);
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s->tick_offset *= NANOSECONDS_PER_SECOND;
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s->tick_offset -= qemu_clock_get_ns(rtc_clock);
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s->tick_offset_vmstate = 0;
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s->alarm_next = 0;
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s->alarm_running = 0;
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s->irq_pending = 0;
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s->irq_enabled = 0;
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}
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static void goldfish_rtc_realize(DeviceState *d, Error **errp)
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{
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SysBusDevice *dev = SYS_BUS_DEVICE(d);
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GoldfishRTCState *s = GOLDFISH_RTC(d);
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memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_rtc_ops, s,
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"goldfish_rtc", 0x24);
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sysbus_init_mmio(dev, &s->iomem);
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sysbus_init_irq(dev, &s->irq);
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s->timer = timer_new_ns(rtc_clock, goldfish_rtc_interrupt, s);
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}
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static void goldfish_rtc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = goldfish_rtc_realize;
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dc->reset = goldfish_rtc_reset;
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dc->vmsd = &goldfish_rtc_vmstate;
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}
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static const TypeInfo goldfish_rtc_info = {
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.name = TYPE_GOLDFISH_RTC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(GoldfishRTCState),
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.class_init = goldfish_rtc_class_init,
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};
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static void goldfish_rtc_register_types(void)
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{
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type_register_static(&goldfish_rtc_info);
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}
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type_init(goldfish_rtc_register_types)
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