xemu/include/exec
Zhang Chen 13af18f222 COLO: Load dirty pages into SVM's RAM cache firstly
We should not load PVM's state directly into SVM, because there maybe some
errors happen when SVM is receving data, which will break SVM.

We need to ensure receving all data before load the state into SVM. We use
an extra memory to cache these data (PVM's ram). The ram cache in secondary side
is initially the same as SVM/PVM's memory. And in the process of checkpoint,
we cache the dirty pages of PVM into this ram cache firstly, so this ram cache
always the same as PVM's memory at every checkpoint, then we flush this cached ram
to SVM after we receive all PVM's state.

Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com>
Signed-off-by: Li Zhijian <lizhijian@cn.fujitsu.com>
Signed-off-by: Zhang Chen <zhangckid@gmail.com>
Signed-off-by: Zhang Chen <chen.zhang@intel.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2018-10-19 11:15:03 +08:00
..
user linux-user: Assert on bad type in thunk_type_align() and thunk_type_size() 2018-05-24 20:46:54 +02:00
address-spaces.h Clean up header guards that don't match their file name 2016-07-12 16:19:16 +02:00
cpu_ldst_template.h trace: switch to modular code generation for sub-directories 2017-01-31 17:11:18 +00:00
cpu_ldst_useronly_template.h linux-user: fix 32bit g2h()/h2g() 2018-08-17 13:56:33 +02:00
cpu_ldst.h linux-user: fix 32bit g2h()/h2g() 2018-08-17 13:56:33 +02:00
cpu-all.h tcg: Define and use new tlb_hit() and tlb_hit_page() functions 2018-07-02 08:02:20 -07:00
cpu-common.h tcg: remove tb_lock 2018-06-15 08:18:48 -10:00
cpu-defs.h cpu-defs.h: Document CPUIOTLBEntry 'addr' field 2018-06-15 15:23:34 +01:00
cputlb.h cputlb: bring back tlb_flush_count under !TLB_DEBUG 2017-10-10 07:37:10 -07:00
exec-all.h accel/tcg: Check whether TLB entry is RAM consistently with how we set it up 2018-08-14 17:17:19 +01:00
gdbstub.h gdbstub: Clarify what gdb_handlesig() is doing 2018-05-25 10:10:55 +02:00
gen-icount.h tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
helper-gen.h tcg: Allow 6 arguments to TCG helpers 2017-12-29 12:43:40 -08:00
helper-head.h tcg: Fix helper function vs host abi for float16 2018-05-31 14:50:51 +01:00
helper-proto.h tcg: Allow 6 arguments to TCG helpers 2017-12-29 12:43:40 -08:00
helper-tcg.h tcg: Allow 6 arguments to TCG helpers 2017-12-29 12:43:40 -08:00
hwaddr.h hw: Clean up includes 2016-06-07 18:19:23 +03:00
ioport.h hw: clean up hw/hw.h includes 2016-05-19 16:42:30 +02:00
log.h disas: Remove unused flags arguments 2017-10-25 11:55:09 +02:00
memattrs.h memory.h: Move MemTxResult type to memattrs.h 2017-09-04 15:21:54 +01:00
memory_ldst_cached.inc.h exec: reintroduce MemoryRegion caching 2018-05-09 00:13:38 +02:00
memory_ldst_phys.inc.h exec: move memory access declarations to a common header, inline *_phys functions 2018-05-09 00:13:38 +02:00
memory_ldst.inc.h exec: move memory access declarations to a common header, inline *_phys functions 2018-05-09 00:13:38 +02:00
memory-internal.h tcg: remove tb_lock 2018-06-15 08:18:48 -10:00
memory.h memory: Remove old_mmio accessors 2018-10-02 19:09:14 +02:00
poison.h ppc: Remove deprecated ppcemb target 2018-08-28 11:31:23 +10:00
ram_addr.h COLO: Load dirty pages into SVM's RAM cache firstly 2018-10-19 11:15:03 +08:00
ramlist.h migration: Poison ramblock loops in migration 2018-06-15 14:40:56 +01:00
semihost.h semihosting: add --semihosting-config arg sub-argument 2015-06-19 14:17:45 +01:00
softmmu-semi.h Clean up decorations and whitespace around header guards 2016-07-12 16:20:46 +02:00
target_page.h migration: Make savevm.c target independent 2017-05-18 19:21:00 +02:00
tb-context.h tcg: remove tb_lock 2018-06-15 08:18:48 -10:00
tb-hash-xx.h tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK 2017-10-24 13:53:41 -07:00
tb-hash.h tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK 2017-10-24 13:53:41 -07:00
tb-lookup.h Clean up includes 2018-02-09 05:05:11 +01:00
translator.h translator: merge max_insns into DisasContextBase 2018-05-09 10:12:21 -07:00