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de91ea92e9
Currently S390PCIIOMMU is a normal struct. Let's make it inherit Object in order to take advantage of QOM. In addition, we move some stuff related to IOMMU from S390PCIBusDevice to S390PCIIOMMU. Signed-off-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com> Acked-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
306 lines
9.4 KiB
C
306 lines
9.4 KiB
C
/*
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* s390 PCI instruction definitions
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*
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* Copyright 2014 IBM Corp.
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* Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
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* Hong Bo Li <lihbbj@cn.ibm.com>
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* Yi Min Zhao <zyimin@cn.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at
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* your option) any later version. See the COPYING file in the top-level
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* directory.
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*/
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#ifndef HW_S390_PCI_INST_H
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#define HW_S390_PCI_INST_H
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#include "s390-pci-bus.h"
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#include "sysemu/dma.h"
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/* CLP common request & response block size */
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#define CLP_BLK_SIZE 4096
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#define PCI_BAR_COUNT 6
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#define PCI_MAX_FUNCTIONS 4096
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typedef struct ClpReqHdr {
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uint16_t len;
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uint16_t cmd;
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} QEMU_PACKED ClpReqHdr;
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typedef struct ClpRspHdr {
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uint16_t len;
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uint16_t rsp;
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} QEMU_PACKED ClpRspHdr;
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/* CLP Response Codes */
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#define CLP_RC_OK 0x0010 /* Command request successfully */
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#define CLP_RC_CMD 0x0020 /* Command code not recognized */
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#define CLP_RC_PERM 0x0030 /* Command not authorized */
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#define CLP_RC_FMT 0x0040 /* Invalid command request format */
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#define CLP_RC_LEN 0x0050 /* Invalid command request length */
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#define CLP_RC_8K 0x0060 /* Command requires 8K LPCB */
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#define CLP_RC_RESNOT0 0x0070 /* Reserved field not zero */
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#define CLP_RC_NODATA 0x0080 /* No data available */
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#define CLP_RC_FC_UNKNOWN 0x0100 /* Function code not recognized */
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/*
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* Call Logical Processor - Command Codes
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*/
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#define CLP_LIST_PCI 0x0002
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#define CLP_QUERY_PCI_FN 0x0003
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#define CLP_QUERY_PCI_FNGRP 0x0004
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#define CLP_SET_PCI_FN 0x0005
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/* PCI function handle list entry */
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typedef struct ClpFhListEntry {
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uint16_t device_id;
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uint16_t vendor_id;
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#define CLP_FHLIST_MASK_CONFIG 0x80000000
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uint32_t config;
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uint32_t fid;
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uint32_t fh;
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} QEMU_PACKED ClpFhListEntry;
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#define CLP_RC_SETPCIFN_FH 0x0101 /* Invalid PCI fn handle */
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#define CLP_RC_SETPCIFN_FHOP 0x0102 /* Fn handle not valid for op */
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#define CLP_RC_SETPCIFN_DMAAS 0x0103 /* Invalid DMA addr space */
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#define CLP_RC_SETPCIFN_RES 0x0104 /* Insufficient resources */
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#define CLP_RC_SETPCIFN_ALRDY 0x0105 /* Fn already in requested state */
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#define CLP_RC_SETPCIFN_ERR 0x0106 /* Fn in permanent error state */
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#define CLP_RC_SETPCIFN_RECPND 0x0107 /* Error recovery pending */
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#define CLP_RC_SETPCIFN_BUSY 0x0108 /* Fn busy */
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#define CLP_RC_LISTPCI_BADRT 0x010a /* Resume token not recognized */
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#define CLP_RC_QUERYPCIFG_PFGID 0x010b /* Unrecognized PFGID */
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/* request or response block header length */
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#define LIST_PCI_HDR_LEN 32
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/* Number of function handles fitting in response block */
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#define CLP_FH_LIST_NR_ENTRIES \
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((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN) \
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/ sizeof(ClpFhListEntry))
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#define CLP_SET_ENABLE_PCI_FN 0 /* Yes, 0 enables it */
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#define CLP_SET_DISABLE_PCI_FN 1 /* Yes, 1 disables it */
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#define CLP_UTIL_STR_LEN 64
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#define CLP_MASK_FMT 0xf0000000
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/* List PCI functions request */
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typedef struct ClpReqListPci {
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ClpReqHdr hdr;
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uint32_t fmt;
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uint64_t reserved1;
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uint64_t resume_token;
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uint64_t reserved2;
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} QEMU_PACKED ClpReqListPci;
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/* List PCI functions response */
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typedef struct ClpRspListPci {
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ClpRspHdr hdr;
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uint32_t fmt;
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uint64_t reserved1;
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uint64_t resume_token;
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uint32_t mdd;
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uint16_t max_fn;
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uint8_t flags;
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uint8_t entry_size;
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ClpFhListEntry fh_list[CLP_FH_LIST_NR_ENTRIES];
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} QEMU_PACKED ClpRspListPci;
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/* Query PCI function request */
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typedef struct ClpReqQueryPci {
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ClpReqHdr hdr;
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uint32_t fmt;
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uint64_t reserved1;
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uint32_t fh; /* function handle */
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uint32_t reserved2;
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uint64_t reserved3;
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} QEMU_PACKED ClpReqQueryPci;
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/* Query PCI function response */
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typedef struct ClpRspQueryPci {
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ClpRspHdr hdr;
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uint32_t fmt;
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uint64_t reserved1;
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uint16_t vfn; /* virtual fn number */
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#define CLP_RSP_QPCI_MASK_UTIL 0x100
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#define CLP_RSP_QPCI_MASK_PFGID 0xff
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uint16_t ug;
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uint32_t fid; /* pci function id */
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uint8_t bar_size[PCI_BAR_COUNT];
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uint16_t pchid;
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uint32_t bar[PCI_BAR_COUNT];
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uint64_t reserved2;
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uint64_t sdma; /* start dma as */
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uint64_t edma; /* end dma as */
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uint32_t reserved3[11];
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uint32_t uid;
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uint8_t util_str[CLP_UTIL_STR_LEN]; /* utility string */
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} QEMU_PACKED ClpRspQueryPci;
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/* Query PCI function group request */
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typedef struct ClpReqQueryPciGrp {
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ClpReqHdr hdr;
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uint32_t fmt;
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uint64_t reserved1;
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#define CLP_REQ_QPCIG_MASK_PFGID 0xff
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uint32_t g;
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uint32_t reserved2;
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uint64_t reserved3;
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} QEMU_PACKED ClpReqQueryPciGrp;
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/* Query PCI function group response */
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typedef struct ClpRspQueryPciGrp {
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ClpRspHdr hdr;
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uint32_t fmt;
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uint64_t reserved1;
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#define CLP_RSP_QPCIG_MASK_NOI 0xfff
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uint16_t i;
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uint8_t version;
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#define CLP_RSP_QPCIG_MASK_FRAME 0x2
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#define CLP_RSP_QPCIG_MASK_REFRESH 0x1
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uint8_t fr;
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uint16_t reserved2;
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uint16_t mui;
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uint64_t reserved3;
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uint64_t dasm; /* dma address space mask */
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uint64_t msia; /* MSI address */
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uint64_t reserved4;
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uint64_t reserved5;
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} QEMU_PACKED ClpRspQueryPciGrp;
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/* Set PCI function request */
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typedef struct ClpReqSetPci {
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ClpReqHdr hdr;
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uint32_t fmt;
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uint64_t reserved1;
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uint32_t fh; /* function handle */
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uint16_t reserved2;
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uint8_t oc; /* operation controls */
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uint8_t ndas; /* number of dma spaces */
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uint64_t reserved3;
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} QEMU_PACKED ClpReqSetPci;
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/* Set PCI function response */
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typedef struct ClpRspSetPci {
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ClpRspHdr hdr;
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uint32_t fmt;
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uint64_t reserved1;
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uint32_t fh; /* function handle */
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uint32_t reserved3;
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uint64_t reserved4;
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} QEMU_PACKED ClpRspSetPci;
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typedef struct ClpReqRspListPci {
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ClpReqListPci request;
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ClpRspListPci response;
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} QEMU_PACKED ClpReqRspListPci;
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typedef struct ClpReqRspSetPci {
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ClpReqSetPci request;
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ClpRspSetPci response;
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} QEMU_PACKED ClpReqRspSetPci;
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typedef struct ClpReqRspQueryPci {
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ClpReqQueryPci request;
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ClpRspQueryPci response;
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} QEMU_PACKED ClpReqRspQueryPci;
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typedef struct ClpReqRspQueryPciGrp {
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ClpReqQueryPciGrp request;
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ClpRspQueryPciGrp response;
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} QEMU_PACKED ClpReqRspQueryPciGrp;
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/* Load/Store status codes */
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#define ZPCI_PCI_ST_FUNC_NOT_ENABLED 4
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#define ZPCI_PCI_ST_FUNC_IN_ERR 8
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#define ZPCI_PCI_ST_BLOCKED 12
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#define ZPCI_PCI_ST_INSUF_RES 16
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#define ZPCI_PCI_ST_INVAL_AS 20
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#define ZPCI_PCI_ST_FUNC_ALREADY_ENABLED 24
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#define ZPCI_PCI_ST_DMA_AS_NOT_ENABLED 28
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#define ZPCI_PCI_ST_2ND_OP_IN_INV_AS 36
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#define ZPCI_PCI_ST_FUNC_NOT_AVAIL 40
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#define ZPCI_PCI_ST_ALREADY_IN_RQ_STATE 44
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/* Load/Store return codes */
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#define ZPCI_PCI_LS_OK 0
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#define ZPCI_PCI_LS_ERR 1
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#define ZPCI_PCI_LS_BUSY 2
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#define ZPCI_PCI_LS_INVAL_HANDLE 3
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/* Modify PCI status codes */
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#define ZPCI_MOD_ST_RES_NOT_AVAIL 4
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#define ZPCI_MOD_ST_INSUF_RES 16
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#define ZPCI_MOD_ST_SEQUENCE 24
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#define ZPCI_MOD_ST_DMAAS_INVAL 28
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#define ZPCI_MOD_ST_FRAME_INVAL 32
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#define ZPCI_MOD_ST_ERROR_RECOVER 40
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/* Modify PCI Function Controls */
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#define ZPCI_MOD_FC_REG_INT 2
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#define ZPCI_MOD_FC_DEREG_INT 3
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#define ZPCI_MOD_FC_REG_IOAT 4
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#define ZPCI_MOD_FC_DEREG_IOAT 5
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#define ZPCI_MOD_FC_REREG_IOAT 6
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#define ZPCI_MOD_FC_RESET_ERROR 7
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#define ZPCI_MOD_FC_RESET_BLOCK 9
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#define ZPCI_MOD_FC_SET_MEASURE 10
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/* Store PCI Function Controls status codes */
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#define ZPCI_STPCIFC_ST_PERM_ERROR 8
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#define ZPCI_STPCIFC_ST_INVAL_DMAAS 28
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#define ZPCI_STPCIFC_ST_ERROR_RECOVER 40
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/* FIB function controls */
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#define ZPCI_FIB_FC_ENABLED 0x80
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#define ZPCI_FIB_FC_ERROR 0x40
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#define ZPCI_FIB_FC_LS_BLOCKED 0x20
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#define ZPCI_FIB_FC_DMAAS_REG 0x10
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/* FIB function controls */
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#define ZPCI_FIB_FC_ENABLED 0x80
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#define ZPCI_FIB_FC_ERROR 0x40
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#define ZPCI_FIB_FC_LS_BLOCKED 0x20
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#define ZPCI_FIB_FC_DMAAS_REG 0x10
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/* Function Information Block */
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typedef struct ZpciFib {
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uint8_t fmt; /* format */
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uint8_t reserved1[7];
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uint8_t fc; /* function controls */
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uint8_t reserved2;
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uint16_t reserved3;
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uint32_t reserved4;
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uint64_t pba; /* PCI base address */
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uint64_t pal; /* PCI address limit */
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uint64_t iota; /* I/O Translation Anchor */
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#define FIB_DATA_ISC(x) (((x) >> 28) & 0x7)
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#define FIB_DATA_NOI(x) (((x) >> 16) & 0xfff)
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#define FIB_DATA_AIBVO(x) (((x) >> 8) & 0x3f)
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#define FIB_DATA_SUM(x) (((x) >> 7) & 0x1)
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#define FIB_DATA_AISBO(x) ((x) & 0x3f)
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uint32_t data;
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uint32_t reserved5;
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uint64_t aibv; /* Adapter int bit vector address */
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uint64_t aisb; /* Adapter int summary bit address */
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uint64_t fmb_addr; /* Function measurement address and key */
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uint32_t reserved6;
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uint32_t gd;
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} QEMU_PACKED ZpciFib;
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int pci_dereg_irqs(S390PCIBusDevice *pbdev);
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void pci_dereg_ioat(S390PCIIOMMU *iommu);
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int clp_service_call(S390CPU *cpu, uint8_t r2);
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int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2);
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int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2);
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int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2);
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int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
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uint8_t ar);
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int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar);
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int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar);
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#endif
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