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https://github.com/xemu-project/xemu.git
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d82310f759
Signed-off-by: cmchao <cmchao@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
726 lines
18 KiB
C
726 lines
18 KiB
C
/*
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* TI OMAP processors GPIO emulation.
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*
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* Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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* Copyright (C) 2007-2009 Nokia Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h"
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#include "omap.h"
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/* General-Purpose I/O */
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struct omap_gpio_s {
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qemu_irq irq;
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qemu_irq *in;
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qemu_irq handler[16];
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uint16_t inputs;
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uint16_t outputs;
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uint16_t dir;
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uint16_t edge;
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uint16_t mask;
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uint16_t ints;
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uint16_t pins;
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};
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static void omap_gpio_set(void *opaque, int line, int level)
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{
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struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
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uint16_t prev = s->inputs;
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if (level)
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s->inputs |= 1 << line;
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else
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s->inputs &= ~(1 << line);
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if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
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(1 << line) & s->dir & ~s->mask) {
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s->ints |= 1 << line;
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qemu_irq_raise(s->irq);
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}
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}
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static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
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{
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struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
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int offset = addr & OMAP_MPUI_REG_MASK;
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switch (offset) {
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case 0x00: /* DATA_INPUT */
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return s->inputs & s->pins;
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case 0x04: /* DATA_OUTPUT */
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return s->outputs;
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case 0x08: /* DIRECTION_CONTROL */
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return s->dir;
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case 0x0c: /* INTERRUPT_CONTROL */
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return s->edge;
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case 0x10: /* INTERRUPT_MASK */
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return s->mask;
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case 0x14: /* INTERRUPT_STATUS */
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return s->ints;
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case 0x18: /* PIN_CONTROL (not in OMAP310) */
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OMAP_BAD_REG(addr);
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return s->pins;
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}
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OMAP_BAD_REG(addr);
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return 0;
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}
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static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
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int offset = addr & OMAP_MPUI_REG_MASK;
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uint16_t diff;
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int ln;
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switch (offset) {
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case 0x00: /* DATA_INPUT */
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OMAP_RO_REG(addr);
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return;
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case 0x04: /* DATA_OUTPUT */
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diff = (s->outputs ^ value) & ~s->dir;
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s->outputs = value;
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while ((ln = ffs(diff))) {
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ln --;
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if (s->handler[ln])
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qemu_set_irq(s->handler[ln], (value >> ln) & 1);
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diff &= ~(1 << ln);
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}
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break;
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case 0x08: /* DIRECTION_CONTROL */
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diff = s->outputs & (s->dir ^ value);
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s->dir = value;
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value = s->outputs & ~s->dir;
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while ((ln = ffs(diff))) {
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ln --;
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if (s->handler[ln])
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qemu_set_irq(s->handler[ln], (value >> ln) & 1);
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diff &= ~(1 << ln);
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}
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break;
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case 0x0c: /* INTERRUPT_CONTROL */
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s->edge = value;
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break;
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case 0x10: /* INTERRUPT_MASK */
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s->mask = value;
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break;
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case 0x14: /* INTERRUPT_STATUS */
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s->ints &= ~value;
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if (!s->ints)
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qemu_irq_lower(s->irq);
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break;
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case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
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OMAP_BAD_REG(addr);
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s->pins = value;
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break;
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default:
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OMAP_BAD_REG(addr);
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return;
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}
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}
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/* *Some* sources say the memory region is 32-bit. */
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static CPUReadMemoryFunc * const omap_gpio_readfn[] = {
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omap_badwidth_read16,
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omap_gpio_read,
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omap_badwidth_read16,
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};
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static CPUWriteMemoryFunc * const omap_gpio_writefn[] = {
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omap_badwidth_write16,
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omap_gpio_write,
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omap_badwidth_write16,
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};
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void omap_gpio_reset(struct omap_gpio_s *s)
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{
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s->inputs = 0;
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s->outputs = ~0;
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s->dir = ~0;
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s->edge = ~0;
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s->mask = ~0;
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s->ints = 0;
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s->pins = ~0;
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}
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struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
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qemu_irq irq, omap_clk clk)
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{
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int iomemtype;
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struct omap_gpio_s *s = (struct omap_gpio_s *)
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qemu_mallocz(sizeof(struct omap_gpio_s));
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s->irq = irq;
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s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);
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omap_gpio_reset(s);
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iomemtype = cpu_register_io_memory(omap_gpio_readfn,
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omap_gpio_writefn, s);
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cpu_register_physical_memory(base, 0x1000, iomemtype);
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return s;
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}
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qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s)
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{
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return s->in;
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}
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void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler)
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{
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if (line >= 16 || line < 0)
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hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
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s->handler[line] = handler;
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}
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/* General-Purpose Interface of OMAP2 */
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struct omap2_gpio_s {
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qemu_irq irq[2];
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qemu_irq wkup;
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qemu_irq *in;
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qemu_irq handler[32];
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uint8_t config[2];
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uint32_t inputs;
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uint32_t outputs;
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uint32_t dir;
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uint32_t level[2];
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uint32_t edge[2];
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uint32_t mask[2];
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uint32_t wumask;
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uint32_t ints[2];
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uint32_t debounce;
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uint8_t delay;
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};
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static inline void omap2_gpio_module_int_update(struct omap2_gpio_s *s,
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int line)
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{
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qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]);
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}
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static void omap2_gpio_module_wake(struct omap2_gpio_s *s, int line)
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{
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if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */
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return;
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if (!(s->config[0] & (3 << 3))) /* Force Idle */
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return;
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if (!(s->wumask & (1 << line)))
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return;
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qemu_irq_raise(s->wkup);
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}
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static inline void omap2_gpio_module_out_update(struct omap2_gpio_s *s,
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uint32_t diff)
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{
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int ln;
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s->outputs ^= diff;
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diff &= ~s->dir;
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while ((ln = ffs(diff))) {
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ln --;
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qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);
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diff &= ~(1 << ln);
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}
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}
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static void omap2_gpio_module_level_update(struct omap2_gpio_s *s, int line)
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{
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s->ints[line] |= s->dir &
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((s->inputs & s->level[1]) | (~s->inputs & s->level[0]));
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omap2_gpio_module_int_update(s, line);
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}
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static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line)
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{
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s->ints[0] |= 1 << line;
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omap2_gpio_module_int_update(s, 0);
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s->ints[1] |= 1 << line;
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omap2_gpio_module_int_update(s, 1);
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omap2_gpio_module_wake(s, line);
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}
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static void omap2_gpio_module_set(void *opaque, int line, int level)
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{
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struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
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if (level) {
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if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1]))
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omap2_gpio_module_int(s, line);
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s->inputs |= 1 << line;
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} else {
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if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0]))
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omap2_gpio_module_int(s, line);
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s->inputs &= ~(1 << line);
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}
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}
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static void omap2_gpio_module_reset(struct omap2_gpio_s *s)
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{
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s->config[0] = 0;
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s->config[1] = 2;
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s->ints[0] = 0;
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s->ints[1] = 0;
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s->mask[0] = 0;
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s->mask[1] = 0;
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s->wumask = 0;
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s->dir = ~0;
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s->level[0] = 0;
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s->level[1] = 0;
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s->edge[0] = 0;
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s->edge[1] = 0;
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s->debounce = 0;
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s->delay = 0;
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}
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static uint32_t omap2_gpio_module_read(void *opaque, target_phys_addr_t addr)
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{
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struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
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switch (addr) {
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case 0x00: /* GPIO_REVISION */
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return 0x18;
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case 0x10: /* GPIO_SYSCONFIG */
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return s->config[0];
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case 0x14: /* GPIO_SYSSTATUS */
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return 0x01;
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case 0x18: /* GPIO_IRQSTATUS1 */
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return s->ints[0];
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case 0x1c: /* GPIO_IRQENABLE1 */
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case 0x60: /* GPIO_CLEARIRQENABLE1 */
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case 0x64: /* GPIO_SETIRQENABLE1 */
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return s->mask[0];
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case 0x20: /* GPIO_WAKEUPENABLE */
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case 0x80: /* GPIO_CLEARWKUENA */
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case 0x84: /* GPIO_SETWKUENA */
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return s->wumask;
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case 0x28: /* GPIO_IRQSTATUS2 */
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return s->ints[1];
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case 0x2c: /* GPIO_IRQENABLE2 */
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case 0x70: /* GPIO_CLEARIRQENABLE2 */
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case 0x74: /* GPIO_SETIREQNEABLE2 */
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return s->mask[1];
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case 0x30: /* GPIO_CTRL */
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return s->config[1];
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case 0x34: /* GPIO_OE */
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return s->dir;
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case 0x38: /* GPIO_DATAIN */
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return s->inputs;
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case 0x3c: /* GPIO_DATAOUT */
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case 0x90: /* GPIO_CLEARDATAOUT */
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case 0x94: /* GPIO_SETDATAOUT */
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return s->outputs;
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case 0x40: /* GPIO_LEVELDETECT0 */
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return s->level[0];
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case 0x44: /* GPIO_LEVELDETECT1 */
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return s->level[1];
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case 0x48: /* GPIO_RISINGDETECT */
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return s->edge[0];
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case 0x4c: /* GPIO_FALLINGDETECT */
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return s->edge[1];
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case 0x50: /* GPIO_DEBOUNCENABLE */
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return s->debounce;
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case 0x54: /* GPIO_DEBOUNCINGTIME */
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return s->delay;
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}
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OMAP_BAD_REG(addr);
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return 0;
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}
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static void omap2_gpio_module_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
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uint32_t diff;
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int ln;
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switch (addr) {
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case 0x00: /* GPIO_REVISION */
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case 0x14: /* GPIO_SYSSTATUS */
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case 0x38: /* GPIO_DATAIN */
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OMAP_RO_REG(addr);
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break;
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case 0x10: /* GPIO_SYSCONFIG */
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if (((value >> 3) & 3) == 3)
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fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__);
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if (value & 2)
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omap2_gpio_module_reset(s);
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s->config[0] = value & 0x1d;
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break;
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case 0x18: /* GPIO_IRQSTATUS1 */
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if (s->ints[0] & value) {
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s->ints[0] &= ~value;
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omap2_gpio_module_level_update(s, 0);
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}
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break;
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case 0x1c: /* GPIO_IRQENABLE1 */
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s->mask[0] = value;
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omap2_gpio_module_int_update(s, 0);
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break;
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case 0x20: /* GPIO_WAKEUPENABLE */
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s->wumask = value;
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break;
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case 0x28: /* GPIO_IRQSTATUS2 */
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if (s->ints[1] & value) {
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s->ints[1] &= ~value;
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omap2_gpio_module_level_update(s, 1);
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}
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break;
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case 0x2c: /* GPIO_IRQENABLE2 */
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s->mask[1] = value;
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omap2_gpio_module_int_update(s, 1);
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break;
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case 0x30: /* GPIO_CTRL */
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s->config[1] = value & 7;
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break;
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case 0x34: /* GPIO_OE */
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diff = s->outputs & (s->dir ^ value);
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s->dir = value;
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value = s->outputs & ~s->dir;
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while ((ln = ffs(diff))) {
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diff &= ~(1 <<-- ln);
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qemu_set_irq(s->handler[ln], (value >> ln) & 1);
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}
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omap2_gpio_module_level_update(s, 0);
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omap2_gpio_module_level_update(s, 1);
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break;
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case 0x3c: /* GPIO_DATAOUT */
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omap2_gpio_module_out_update(s, s->outputs ^ value);
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break;
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case 0x40: /* GPIO_LEVELDETECT0 */
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s->level[0] = value;
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omap2_gpio_module_level_update(s, 0);
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omap2_gpio_module_level_update(s, 1);
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break;
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case 0x44: /* GPIO_LEVELDETECT1 */
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s->level[1] = value;
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omap2_gpio_module_level_update(s, 0);
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omap2_gpio_module_level_update(s, 1);
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break;
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case 0x48: /* GPIO_RISINGDETECT */
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s->edge[0] = value;
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break;
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case 0x4c: /* GPIO_FALLINGDETECT */
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s->edge[1] = value;
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break;
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case 0x50: /* GPIO_DEBOUNCENABLE */
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s->debounce = value;
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break;
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case 0x54: /* GPIO_DEBOUNCINGTIME */
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s->delay = value;
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break;
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case 0x60: /* GPIO_CLEARIRQENABLE1 */
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s->mask[0] &= ~value;
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omap2_gpio_module_int_update(s, 0);
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break;
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case 0x64: /* GPIO_SETIRQENABLE1 */
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s->mask[0] |= value;
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omap2_gpio_module_int_update(s, 0);
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break;
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case 0x70: /* GPIO_CLEARIRQENABLE2 */
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s->mask[1] &= ~value;
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omap2_gpio_module_int_update(s, 1);
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break;
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case 0x74: /* GPIO_SETIREQNEABLE2 */
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s->mask[1] |= value;
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omap2_gpio_module_int_update(s, 1);
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break;
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case 0x80: /* GPIO_CLEARWKUENA */
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s->wumask &= ~value;
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break;
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case 0x84: /* GPIO_SETWKUENA */
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s->wumask |= value;
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break;
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case 0x90: /* GPIO_CLEARDATAOUT */
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omap2_gpio_module_out_update(s, s->outputs & value);
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break;
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case 0x94: /* GPIO_SETDATAOUT */
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omap2_gpio_module_out_update(s, ~s->outputs & value);
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break;
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default:
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OMAP_BAD_REG(addr);
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return;
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}
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}
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static uint32_t omap2_gpio_module_readp(void *opaque, target_phys_addr_t addr)
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{
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return omap2_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3);
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}
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static void omap2_gpio_module_writep(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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uint32_t cur = 0;
|
|
uint32_t mask = 0xffff;
|
|
|
|
switch (addr & ~3) {
|
|
case 0x00: /* GPIO_REVISION */
|
|
case 0x14: /* GPIO_SYSSTATUS */
|
|
case 0x38: /* GPIO_DATAIN */
|
|
OMAP_RO_REG(addr);
|
|
break;
|
|
|
|
case 0x10: /* GPIO_SYSCONFIG */
|
|
case 0x1c: /* GPIO_IRQENABLE1 */
|
|
case 0x20: /* GPIO_WAKEUPENABLE */
|
|
case 0x2c: /* GPIO_IRQENABLE2 */
|
|
case 0x30: /* GPIO_CTRL */
|
|
case 0x34: /* GPIO_OE */
|
|
case 0x3c: /* GPIO_DATAOUT */
|
|
case 0x40: /* GPIO_LEVELDETECT0 */
|
|
case 0x44: /* GPIO_LEVELDETECT1 */
|
|
case 0x48: /* GPIO_RISINGDETECT */
|
|
case 0x4c: /* GPIO_FALLINGDETECT */
|
|
case 0x50: /* GPIO_DEBOUNCENABLE */
|
|
case 0x54: /* GPIO_DEBOUNCINGTIME */
|
|
cur = omap2_gpio_module_read(opaque, addr & ~3) &
|
|
~(mask << ((addr & 3) << 3));
|
|
|
|
/* Fall through. */
|
|
case 0x18: /* GPIO_IRQSTATUS1 */
|
|
case 0x28: /* GPIO_IRQSTATUS2 */
|
|
case 0x60: /* GPIO_CLEARIRQENABLE1 */
|
|
case 0x64: /* GPIO_SETIRQENABLE1 */
|
|
case 0x70: /* GPIO_CLEARIRQENABLE2 */
|
|
case 0x74: /* GPIO_SETIREQNEABLE2 */
|
|
case 0x80: /* GPIO_CLEARWKUENA */
|
|
case 0x84: /* GPIO_SETWKUENA */
|
|
case 0x90: /* GPIO_CLEARDATAOUT */
|
|
case 0x94: /* GPIO_SETDATAOUT */
|
|
value <<= (addr & 3) << 3;
|
|
omap2_gpio_module_write(opaque, addr, cur | value);
|
|
break;
|
|
|
|
default:
|
|
OMAP_BAD_REG(addr);
|
|
return;
|
|
}
|
|
}
|
|
|
|
static CPUReadMemoryFunc * const omap2_gpio_module_readfn[] = {
|
|
omap2_gpio_module_readp,
|
|
omap2_gpio_module_readp,
|
|
omap2_gpio_module_read,
|
|
};
|
|
|
|
static CPUWriteMemoryFunc * const omap2_gpio_module_writefn[] = {
|
|
omap2_gpio_module_writep,
|
|
omap2_gpio_module_writep,
|
|
omap2_gpio_module_write,
|
|
};
|
|
|
|
static void omap2_gpio_module_init(struct omap2_gpio_s *s,
|
|
struct omap_target_agent_s *ta, int region,
|
|
qemu_irq mpu, qemu_irq dsp, qemu_irq wkup,
|
|
omap_clk fclk, omap_clk iclk)
|
|
{
|
|
int iomemtype;
|
|
|
|
s->irq[0] = mpu;
|
|
s->irq[1] = dsp;
|
|
s->wkup = wkup;
|
|
s->in = qemu_allocate_irqs(omap2_gpio_module_set, s, 32);
|
|
|
|
iomemtype = l4_register_io_memory(omap2_gpio_module_readfn,
|
|
omap2_gpio_module_writefn, s);
|
|
omap_l4_attach(ta, region, iomemtype);
|
|
}
|
|
|
|
struct omap_gpif_s {
|
|
struct omap2_gpio_s module[5];
|
|
int modules;
|
|
|
|
int autoidle;
|
|
int gpo;
|
|
};
|
|
|
|
void omap_gpif_reset(struct omap_gpif_s *s)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < s->modules; i ++)
|
|
omap2_gpio_module_reset(s->module + i);
|
|
|
|
s->autoidle = 0;
|
|
s->gpo = 0;
|
|
}
|
|
|
|
static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
|
|
|
|
switch (addr) {
|
|
case 0x00: /* IPGENERICOCPSPL_REVISION */
|
|
return 0x18;
|
|
|
|
case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
|
|
return s->autoidle;
|
|
|
|
case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
|
|
return 0x01;
|
|
|
|
case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
|
|
return 0x00;
|
|
|
|
case 0x40: /* IPGENERICOCPSPL_GPO */
|
|
return s->gpo;
|
|
|
|
case 0x50: /* IPGENERICOCPSPL_GPI */
|
|
return 0x00;
|
|
}
|
|
|
|
OMAP_BAD_REG(addr);
|
|
return 0;
|
|
}
|
|
|
|
static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr,
|
|
uint32_t value)
|
|
{
|
|
struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
|
|
|
|
switch (addr) {
|
|
case 0x00: /* IPGENERICOCPSPL_REVISION */
|
|
case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
|
|
case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
|
|
case 0x50: /* IPGENERICOCPSPL_GPI */
|
|
OMAP_RO_REG(addr);
|
|
break;
|
|
|
|
case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
|
|
if (value & (1 << 1)) /* SOFTRESET */
|
|
omap_gpif_reset(s);
|
|
s->autoidle = value & 1;
|
|
break;
|
|
|
|
case 0x40: /* IPGENERICOCPSPL_GPO */
|
|
s->gpo = value & 1;
|
|
break;
|
|
|
|
default:
|
|
OMAP_BAD_REG(addr);
|
|
return;
|
|
}
|
|
}
|
|
|
|
static CPUReadMemoryFunc * const omap_gpif_top_readfn[] = {
|
|
omap_gpif_top_read,
|
|
omap_gpif_top_read,
|
|
omap_gpif_top_read,
|
|
};
|
|
|
|
static CPUWriteMemoryFunc * const omap_gpif_top_writefn[] = {
|
|
omap_gpif_top_write,
|
|
omap_gpif_top_write,
|
|
omap_gpif_top_write,
|
|
};
|
|
|
|
struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
|
|
qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules)
|
|
{
|
|
int iomemtype, i;
|
|
struct omap_gpif_s *s = (struct omap_gpif_s *)
|
|
qemu_mallocz(sizeof(struct omap_gpif_s));
|
|
int region[4] = { 0, 2, 4, 5 };
|
|
|
|
s->modules = modules;
|
|
for (i = 0; i < modules; i ++)
|
|
omap2_gpio_module_init(s->module + i, ta, region[i],
|
|
irq[i], NULL, NULL, fclk[i], iclk);
|
|
|
|
omap_gpif_reset(s);
|
|
|
|
iomemtype = l4_register_io_memory(omap_gpif_top_readfn,
|
|
omap_gpif_top_writefn, s);
|
|
omap_l4_attach(ta, 1, iomemtype);
|
|
|
|
return s;
|
|
}
|
|
|
|
qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start)
|
|
{
|
|
if (start >= s->modules * 32 || start < 0)
|
|
hw_error("%s: No GPIO line %i\n", __FUNCTION__, start);
|
|
return s->module[start >> 5].in + (start & 31);
|
|
}
|
|
|
|
void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler)
|
|
{
|
|
if (line >= s->modules * 32 || line < 0)
|
|
hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
|
|
s->module[line >> 5].handler[line & 31] = handler;
|
|
}
|