Paul A. Clarke bc7a45ab88 ppc: Add support for 'mffsce' instruction ... ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR) instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl. This patch adds support for 'mffsce' instruction. 'mffsce' is identical to 'mffs', except that it also clears the exception enable bits in the FPSCR. On CPUs without support for 'mffsce' (below ISA 3.0), the instruction will execute identically to 'mffs'. Signed-off-by: Paul A. Clarke <pc@us.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1568817082-1384-1-git-send-email-pc@us.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>		2019-10-04 10:25:23 +10:00
..
dfp-impl.inc.c	target/ppc: move FP and VMX registers into aligned vsr register array	2019-01-09 09:28:14 +11:00
dfp-ops.inc.c	Move target-* CPU file into a target/ folder	2016-12-20 21:52:12 +01:00
fp-impl.inc.c	ppc: Add support for 'mffsce' instruction	2019-10-04 10:25:23 +10:00
fp-ops.inc.c	ppc: Add support for 'mffsce' instruction	2019-10-04 10:25:23 +10:00
spe-impl.inc.c	target/ppc: Use tcg_gen_abs_i32	2019-05-13 22:52:08 +00:00
spe-ops.inc.c	Move target-* CPU file into a target/ folder	2016-12-20 21:52:12 +01:00
vmx-impl.inc.c	target/ppc: Refactor emulation of vmrgew and vmrgow instructions	2019-08-29 09:46:07 +10:00
vmx-ops.inc.c	Changes requirement for "vsubsbs" instruction	2018-12-21 09:29:12 +11:00
vsx-impl.inc.c	ppc: Fix xsmaddmdp and friends	2019-08-29 09:46:07 +10:00
vsx-ops.inc.c	target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro	2019-07-02 09:43:58 +10:00