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8cba80c3a0
This patch implements a pci bus for s390x together with infrastructure to generate and handle hotplug events, to configure/unconfigure via sclp instruction, to do iommu translations and provide s390 support for MSI/MSI-X notification processing. Signed-off-by: Frank Blaschka <frank.blaschka@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
252 lines
7.2 KiB
C
252 lines
7.2 KiB
C
/*
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* s390 PCI BUS definitions
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*
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* Copyright 2014 IBM Corp.
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* Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
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* Hong Bo Li <lihbbj@cn.ibm.com>
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* Yi Min Zhao <zyimin@cn.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at
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* your option) any later version. See the COPYING file in the top-level
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* directory.
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*/
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#ifndef HW_S390_PCI_BUS_H
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#define HW_S390_PCI_BUS_H
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#include <hw/pci/pci.h>
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#include <hw/pci/pci_host.h>
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#include "hw/s390x/sclp.h"
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#include "hw/s390x/s390_flic.h"
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#include "hw/s390x/css.h"
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#define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
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#define FH_VIRT 0x00ff0000
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#define ENABLE_BIT_OFFSET 31
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#define S390_PCIPT_ADAPTER 2
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#define S390_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(S390pciState, (obj), TYPE_S390_PCI_HOST_BRIDGE)
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#define HP_EVENT_TO_CONFIGURED 0x0301
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#define HP_EVENT_RESERVED_TO_STANDBY 0x0302
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#define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
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#define HP_EVENT_STANDBY_TO_RESERVED 0x0308
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#define ERR_EVENT_INVALAS 0x1
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#define ERR_EVENT_OORANGE 0x2
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#define ERR_EVENT_INVALTF 0x3
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#define ERR_EVENT_TPROTE 0x4
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#define ERR_EVENT_APROTE 0x5
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#define ERR_EVENT_KEYE 0x6
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#define ERR_EVENT_INVALTE 0x7
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#define ERR_EVENT_INVALTL 0x8
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#define ERR_EVENT_TT 0x9
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#define ERR_EVENT_INVALMS 0xa
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#define ERR_EVENT_SERR 0xb
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#define ERR_EVENT_NOMSI 0x10
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#define ERR_EVENT_INVALBV 0x11
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#define ERR_EVENT_AIBV 0x12
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#define ERR_EVENT_AIRERR 0x13
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#define ERR_EVENT_FMBA 0x2a
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#define ERR_EVENT_FMBUP 0x2b
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#define ERR_EVENT_FMBPRO 0x2c
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#define ERR_EVENT_CCONF 0x30
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#define ERR_EVENT_SERVAC 0x3a
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#define ERR_EVENT_PERMERR 0x3b
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#define ERR_EVENT_Q_BIT 0x2
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#define ERR_EVENT_MVN_OFFSET 16
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#define ZPCI_MSI_VEC_BITS 11
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#define ZPCI_MSI_VEC_MASK 0x7ff
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#define ZPCI_MSI_ADDR 0xfe00000000000000ULL
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#define ZPCI_SDMA_ADDR 0x100000000ULL
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#define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
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#define PAGE_SHIFT 12
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#define PAGE_MASK (~(PAGE_SIZE-1))
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#define PAGE_DEFAULT_ACC 0
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#define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4)
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/* I/O Translation Anchor (IOTA) */
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enum ZpciIoatDtype {
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ZPCI_IOTA_STO = 0,
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ZPCI_IOTA_RTTO = 1,
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ZPCI_IOTA_RSTO = 2,
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ZPCI_IOTA_RFTO = 3,
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ZPCI_IOTA_PFAA = 4,
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ZPCI_IOTA_IOPFAA = 5,
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ZPCI_IOTA_IOPTO = 7
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};
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#define ZPCI_IOTA_IOT_ENABLED 0x800ULL
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#define ZPCI_IOTA_DT_ST (ZPCI_IOTA_STO << 2)
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#define ZPCI_IOTA_DT_RT (ZPCI_IOTA_RTTO << 2)
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#define ZPCI_IOTA_DT_RS (ZPCI_IOTA_RSTO << 2)
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#define ZPCI_IOTA_DT_RF (ZPCI_IOTA_RFTO << 2)
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#define ZPCI_IOTA_DT_PF (ZPCI_IOTA_PFAA << 2)
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#define ZPCI_IOTA_FS_4K 0
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#define ZPCI_IOTA_FS_1M 1
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#define ZPCI_IOTA_FS_2G 2
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#define ZPCI_KEY (PAGE_DEFAULT_KEY << 5)
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#define ZPCI_IOTA_STO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
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#define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
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#define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
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#define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
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#define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\
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ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)
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/* I/O Region and segment tables */
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#define ZPCI_INDEX_MASK 0x7ffULL
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#define ZPCI_TABLE_TYPE_MASK 0xc
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#define ZPCI_TABLE_TYPE_RFX 0xc
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#define ZPCI_TABLE_TYPE_RSX 0x8
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#define ZPCI_TABLE_TYPE_RTX 0x4
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#define ZPCI_TABLE_TYPE_SX 0x0
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#define ZPCI_TABLE_LEN_RFX 0x3
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#define ZPCI_TABLE_LEN_RSX 0x3
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#define ZPCI_TABLE_LEN_RTX 0x3
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#define ZPCI_TABLE_OFFSET_MASK 0xc0
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#define ZPCI_TABLE_SIZE 0x4000
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#define ZPCI_TABLE_ALIGN ZPCI_TABLE_SIZE
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#define ZPCI_TABLE_ENTRY_SIZE (sizeof(unsigned long))
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#define ZPCI_TABLE_ENTRIES (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
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#define ZPCI_TABLE_BITS 11
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#define ZPCI_PT_BITS 8
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#define ZPCI_ST_SHIFT (ZPCI_PT_BITS + PAGE_SHIFT)
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#define ZPCI_RT_SHIFT (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
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#define ZPCI_RTE_FLAG_MASK 0x3fffULL
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#define ZPCI_RTE_ADDR_MASK (~ZPCI_RTE_FLAG_MASK)
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#define ZPCI_STE_FLAG_MASK 0x7ffULL
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#define ZPCI_STE_ADDR_MASK (~ZPCI_STE_FLAG_MASK)
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/* I/O Page tables */
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#define ZPCI_PTE_VALID_MASK 0x400
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#define ZPCI_PTE_INVALID 0x400
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#define ZPCI_PTE_VALID 0x000
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#define ZPCI_PT_SIZE 0x800
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#define ZPCI_PT_ALIGN ZPCI_PT_SIZE
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#define ZPCI_PT_ENTRIES (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
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#define ZPCI_PT_MASK (ZPCI_PT_ENTRIES - 1)
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#define ZPCI_PTE_FLAG_MASK 0xfffULL
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#define ZPCI_PTE_ADDR_MASK (~ZPCI_PTE_FLAG_MASK)
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/* Shared bits */
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#define ZPCI_TABLE_VALID 0x00
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#define ZPCI_TABLE_INVALID 0x20
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#define ZPCI_TABLE_PROTECTED 0x200
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#define ZPCI_TABLE_UNPROTECTED 0x000
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#define ZPCI_TABLE_VALID_MASK 0x20
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#define ZPCI_TABLE_PROT_MASK 0x200
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typedef struct SeiContainer {
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QTAILQ_ENTRY(SeiContainer) link;
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uint32_t fid;
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uint32_t fh;
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uint8_t cc;
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uint16_t pec;
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uint64_t faddr;
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uint32_t e;
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} SeiContainer;
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typedef struct PciCcdfErr {
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uint32_t reserved1;
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uint32_t fh;
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uint32_t fid;
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uint32_t e;
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uint64_t faddr;
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uint32_t reserved3;
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uint16_t reserved4;
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uint16_t pec;
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} QEMU_PACKED PciCcdfErr;
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typedef struct PciCcdfAvail {
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uint32_t reserved1;
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uint32_t fh;
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uint32_t fid;
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uint32_t reserved2;
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uint32_t reserved3;
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uint32_t reserved4;
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uint32_t reserved5;
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uint16_t reserved6;
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uint16_t pec;
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} QEMU_PACKED PciCcdfAvail;
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typedef struct ChscSeiNt2Res {
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uint16_t length;
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uint16_t code;
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uint16_t reserved1;
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uint8_t reserved2;
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uint8_t nt;
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uint8_t flags;
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uint8_t reserved3;
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uint8_t reserved4;
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uint8_t cc;
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uint32_t reserved5[13];
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uint8_t ccdf[4016];
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} QEMU_PACKED ChscSeiNt2Res;
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typedef struct PciCfgSccb {
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SCCBHeader header;
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uint8_t atype;
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uint8_t reserved1;
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uint16_t reserved2;
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uint32_t aid;
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} QEMU_PACKED PciCfgSccb;
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typedef struct S390MsixInfo {
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bool available;
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uint8_t table_bar;
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uint8_t pba_bar;
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uint16_t entries;
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uint32_t table_offset;
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uint32_t pba_offset;
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} S390MsixInfo;
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typedef struct S390PCIBusDevice {
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PCIDevice *pdev;
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bool configured;
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bool error_state;
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bool lgstg_blocked;
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uint32_t fh;
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uint32_t fid;
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uint64_t g_iota;
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uint64_t pba;
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uint64_t pal;
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uint64_t fmb_addr;
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uint8_t isc;
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uint16_t noi;
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uint8_t sum;
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S390MsixInfo msix;
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AdapterRoutes routes;
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AddressSpace as;
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MemoryRegion mr;
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} S390PCIBusDevice;
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typedef struct S390pciState {
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PCIHostState parent_obj;
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S390PCIBusDevice pbdev[PCI_SLOT_MAX];
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AddressSpace msix_notify_as;
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MemoryRegion msix_notify_mr;
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QTAILQ_HEAD(, SeiContainer) pending_sei;
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} S390pciState;
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int chsc_sei_nt2_get_event(void *res);
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int chsc_sei_nt2_have_event(void);
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void s390_pci_sclp_configure(int configure, SCCB *sccb);
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S390PCIBusDevice *s390_pci_find_dev_by_idx(uint32_t idx);
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S390PCIBusDevice *s390_pci_find_dev_by_fh(uint32_t fh);
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S390PCIBusDevice *s390_pci_find_dev_by_fid(uint32_t fid);
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#endif
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