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1635bdfa78
This tells the sysbus code it need not use IO_MEM_UNASSIGNED. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
118 lines
3.3 KiB
C
118 lines
3.3 KiB
C
/*
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* ARM11MPCore internal peripheral emulation.
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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/* ??? The MPCore TRM says the on-chip controller has 224 external IRQ lines
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(+ 32 internal). However my test chip only exposes/reports 32.
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More importantly Linux falls over if more than 32 are present! */
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#define GIC_NIRQ 64
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#include "mpcore.c"
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/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
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controllers. The output of these, plus some of the raw input lines
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are fed into a single SMP-aware interrupt controller on the CPU. */
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typedef struct {
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SysBusDevice busdev;
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SysBusDevice *priv;
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qemu_irq cpuic[32];
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qemu_irq rvic[4][64];
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uint32_t num_cpu;
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} mpcore_rirq_state;
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/* Map baseboard IRQs onto CPU IRQ lines. */
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static const int mpcore_irq_map[32] = {
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-1, -1, -1, -1, 1, 2, -1, -1,
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-1, -1, 6, -1, 4, 5, -1, -1,
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-1, 14, 15, 0, 7, 8, -1, -1,
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-1, -1, -1, -1, 9, 3, -1, -1,
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};
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static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
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{
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mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
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int i;
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for (i = 0; i < 4; i++) {
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qemu_set_irq(s->rvic[i][irq], level);
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}
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if (irq < 32) {
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irq = mpcore_irq_map[irq];
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if (irq >= 0) {
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qemu_set_irq(s->cpuic[irq], level);
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}
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}
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}
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static void mpcore_rirq_map(SysBusDevice *dev, target_phys_addr_t base)
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{
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mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);
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sysbus_mmio_map(s->priv, 0, base);
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}
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static void mpcore_rirq_unmap(SysBusDevice *dev, target_phys_addr_t base)
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{
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/* nothing to do */
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}
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static int realview_mpcore_init(SysBusDevice *dev)
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{
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mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);
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DeviceState *gic;
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DeviceState *priv;
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int n;
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int i;
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priv = qdev_create(NULL, "arm11mpcore_priv");
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qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
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qdev_init_nofail(priv);
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s->priv = sysbus_from_qdev(priv);
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sysbus_pass_irq(dev, s->priv);
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for (i = 0; i < 32; i++) {
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s->cpuic[i] = qdev_get_gpio_in(priv, i);
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}
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/* ??? IRQ routing is hardcoded to "normal" mode. */
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for (n = 0; n < 4; n++) {
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gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000,
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s->cpuic[10 + n]);
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for (i = 0; i < 64; i++) {
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s->rvic[n][i] = qdev_get_gpio_in(gic, i);
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}
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}
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qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
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sysbus_init_mmio_cb2(dev, mpcore_rirq_map, mpcore_rirq_unmap);
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return 0;
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}
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static SysBusDeviceInfo mpcore_rirq_info = {
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.init = realview_mpcore_init,
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.qdev.name = "realview_mpcore",
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.qdev.size = sizeof(mpcore_rirq_state),
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static SysBusDeviceInfo mpcore_priv_info = {
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.init = mpcore_priv_init,
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.qdev.name = "arm11mpcore_priv",
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.qdev.size = sizeof(mpcore_priv_state),
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static void arm11mpcore_register_devices(void)
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{
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sysbus_register_withprop(&mpcore_rirq_info);
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sysbus_register_withprop(&mpcore_priv_info);
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}
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device_init(arm11mpcore_register_devices)
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