mirror of
https://github.com/xemu-project/xemu.git
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426f03482c
* Add user-mode CSR defininitions. * Reorder CSR definitions to match the specification. * Change H mode interrupt comment to 'reserved'. * Remove unused X_COP interrupt. * Add user-mode interrupts. * Remove erroneous until comments on machine mode interrupts. * Move together paging mode and page table bit definitions. * Move together interrupt and exception cause definitions. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
724 lines
22 KiB
C
724 lines
22 KiB
C
/*
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* RISC-V Emulation Helpers for QEMU.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "qemu/main-loop.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#ifndef CONFIG_USER_ONLY
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#if defined(TARGET_RISCV32)
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static const char valid_vm_1_09[16] = {
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[VM_1_09_MBARE] = 1,
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[VM_1_09_SV32] = 1,
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};
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static const char valid_vm_1_10[16] = {
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[VM_1_10_MBARE] = 1,
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[VM_1_10_SV32] = 1
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};
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#elif defined(TARGET_RISCV64)
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static const char valid_vm_1_09[16] = {
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[VM_1_09_MBARE] = 1,
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[VM_1_09_SV39] = 1,
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[VM_1_09_SV48] = 1,
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};
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static const char valid_vm_1_10[16] = {
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[VM_1_10_MBARE] = 1,
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[VM_1_10_SV39] = 1,
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[VM_1_10_SV48] = 1,
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[VM_1_10_SV57] = 1
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};
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#endif
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static int validate_vm(CPURISCVState *env, target_ulong vm)
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{
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return (env->priv_ver >= PRIV_VERSION_1_10_0) ?
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valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf];
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}
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#endif
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/* Exceptions processing helpers */
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void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
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uint32_t exception, uintptr_t pc)
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{
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CPUState *cs = CPU(riscv_env_get_cpu(env));
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qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception);
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cs->exception_index = exception;
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cpu_loop_exit_restore(cs, pc);
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}
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void helper_raise_exception(CPURISCVState *env, uint32_t exception)
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{
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do_raise_exception_err(env, exception, 0);
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}
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static void validate_mstatus_fs(CPURISCVState *env, uintptr_t ra)
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{
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#ifndef CONFIG_USER_ONLY
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if (!(env->mstatus & MSTATUS_FS)) {
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do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, ra);
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}
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#endif
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}
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/*
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* Handle writes to CSRs and any resulting special behavior
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*
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* Adapted from Spike's processor_t::set_csr
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*/
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void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
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target_ulong csrno)
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{
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#ifndef CONFIG_USER_ONLY
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uint64_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP;
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uint64_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
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#endif
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switch (csrno) {
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case CSR_FFLAGS:
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validate_mstatus_fs(env, GETPC());
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cpu_riscv_set_fflags(env, val_to_write & (FSR_AEXC >> FSR_AEXC_SHIFT));
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break;
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case CSR_FRM:
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validate_mstatus_fs(env, GETPC());
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env->frm = val_to_write & (FSR_RD >> FSR_RD_SHIFT);
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break;
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case CSR_FCSR:
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validate_mstatus_fs(env, GETPC());
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env->frm = (val_to_write & FSR_RD) >> FSR_RD_SHIFT;
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cpu_riscv_set_fflags(env, (val_to_write & FSR_AEXC) >> FSR_AEXC_SHIFT);
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break;
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#ifndef CONFIG_USER_ONLY
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case CSR_MSTATUS: {
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target_ulong mstatus = env->mstatus;
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target_ulong mask = 0;
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target_ulong mpp = get_field(val_to_write, MSTATUS_MPP);
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/* flush tlb on mstatus fields that affect VM */
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if (env->priv_ver <= PRIV_VERSION_1_09_1) {
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if ((val_to_write ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP |
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MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) {
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helper_tlb_flush(env);
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}
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mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
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MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
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MSTATUS_MPP | MSTATUS_MXR |
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(validate_vm(env, get_field(val_to_write, MSTATUS_VM)) ?
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MSTATUS_VM : 0);
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}
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if (env->priv_ver >= PRIV_VERSION_1_10_0) {
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if ((val_to_write ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP |
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MSTATUS_MPRV | MSTATUS_SUM)) {
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helper_tlb_flush(env);
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}
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mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
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MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
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MSTATUS_MPP | MSTATUS_MXR;
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}
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/* silenty discard mstatus.mpp writes for unsupported modes */
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if (mpp == PRV_H ||
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(!riscv_has_ext(env, RVS) && mpp == PRV_S) ||
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(!riscv_has_ext(env, RVU) && mpp == PRV_U)) {
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mask &= ~MSTATUS_MPP;
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}
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mstatus = (mstatus & ~mask) | (val_to_write & mask);
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/* Note: this is a workaround for an issue where mstatus.FS
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does not report dirty after floating point operations
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that modify floating point state. This workaround is
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technically compliant with the RISC-V Privileged
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specification as it is legal to return only off, or dirty.
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at the expense of extra floating point save/restore. */
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/* FP is always dirty or off */
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if (mstatus & MSTATUS_FS) {
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mstatus |= MSTATUS_FS;
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}
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int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
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((mstatus & MSTATUS_XS) == MSTATUS_XS);
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mstatus = set_field(mstatus, MSTATUS_SD, dirty);
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env->mstatus = mstatus;
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break;
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}
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case CSR_MIP: {
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/*
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* Since the writeable bits in MIP are not set asynchrously by the
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* CLINT, no additional locking is needed for read-modifiy-write
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* CSR operations
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*/
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qemu_mutex_lock_iothread();
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RISCVCPU *cpu = riscv_env_get_cpu(env);
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riscv_cpu_update_mip(cpu, MIP_SSIP | MIP_STIP,
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(val_to_write & (MIP_SSIP | MIP_STIP)));
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/*
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* csrs, csrc on mip.SEIP is not decomposable into separate read and
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* write steps, so a different implementation is needed
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*/
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qemu_mutex_unlock_iothread();
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break;
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}
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case CSR_MIE: {
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env->mie = (env->mie & ~all_ints) |
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(val_to_write & all_ints);
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break;
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}
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case CSR_MIDELEG:
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env->mideleg = (env->mideleg & ~delegable_ints)
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| (val_to_write & delegable_ints);
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break;
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case CSR_MEDELEG: {
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target_ulong mask = 0;
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mask |= 1ULL << (RISCV_EXCP_INST_ADDR_MIS);
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mask |= 1ULL << (RISCV_EXCP_INST_ACCESS_FAULT);
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mask |= 1ULL << (RISCV_EXCP_ILLEGAL_INST);
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mask |= 1ULL << (RISCV_EXCP_BREAKPOINT);
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mask |= 1ULL << (RISCV_EXCP_LOAD_ADDR_MIS);
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mask |= 1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT);
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mask |= 1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS);
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mask |= 1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT);
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mask |= 1ULL << (RISCV_EXCP_U_ECALL);
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mask |= 1ULL << (RISCV_EXCP_S_ECALL);
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mask |= 1ULL << (RISCV_EXCP_H_ECALL);
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mask |= 1ULL << (RISCV_EXCP_M_ECALL);
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mask |= 1ULL << (RISCV_EXCP_INST_PAGE_FAULT);
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mask |= 1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT);
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mask |= 1ULL << (RISCV_EXCP_STORE_PAGE_FAULT);
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env->medeleg = (env->medeleg & ~mask)
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| (val_to_write & mask);
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break;
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}
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case CSR_MINSTRET:
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/* minstret is WARL so unsupported writes are ignored */
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break;
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case CSR_MCYCLE:
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/* mcycle is WARL so unsupported writes are ignored */
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break;
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#if defined(TARGET_RISCV32)
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case CSR_MINSTRETH:
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/* minstreth is WARL so unsupported writes are ignored */
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break;
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case CSR_MCYCLEH:
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/* mcycleh is WARL so unsupported writes are ignored */
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break;
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#endif
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case CSR_MUCOUNTEREN:
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if (env->priv_ver <= PRIV_VERSION_1_09_1) {
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env->scounteren = val_to_write;
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break;
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} else {
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goto do_illegal;
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}
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case CSR_MSCOUNTEREN:
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if (env->priv_ver <= PRIV_VERSION_1_09_1) {
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env->mcounteren = val_to_write;
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break;
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} else {
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goto do_illegal;
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}
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case CSR_SSTATUS: {
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target_ulong ms = env->mstatus;
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target_ulong mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE
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| SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS
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| SSTATUS_SUM | SSTATUS_SD;
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if (env->priv_ver >= PRIV_VERSION_1_10_0) {
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mask |= SSTATUS_MXR;
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}
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ms = (ms & ~mask) | (val_to_write & mask);
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csr_write_helper(env, ms, CSR_MSTATUS);
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break;
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}
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case CSR_SIP: {
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qemu_mutex_lock_iothread();
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target_ulong next_mip = (env->mip & ~env->mideleg)
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| (val_to_write & env->mideleg);
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qemu_mutex_unlock_iothread();
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csr_write_helper(env, next_mip, CSR_MIP);
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break;
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}
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case CSR_SIE: {
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target_ulong next_mie = (env->mie & ~env->mideleg)
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| (val_to_write & env->mideleg);
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csr_write_helper(env, next_mie, CSR_MIE);
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break;
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}
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case CSR_SATP: /* CSR_SPTBR */ {
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if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
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break;
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}
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if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val_to_write ^ env->sptbr))
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{
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helper_tlb_flush(env);
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env->sptbr = val_to_write & (((target_ulong)
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1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1);
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}
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if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
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validate_vm(env, get_field(val_to_write, SATP_MODE)) &&
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((val_to_write ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
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{
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helper_tlb_flush(env);
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env->satp = val_to_write;
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}
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break;
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}
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case CSR_SEPC:
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env->sepc = val_to_write;
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break;
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case CSR_STVEC:
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/* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
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if ((val_to_write & 3) == 0) {
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env->stvec = val_to_write >> 2 << 2;
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} else {
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qemu_log_mask(LOG_UNIMP,
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"CSR_STVEC: vectored traps not supported\n");
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}
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break;
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case CSR_SCOUNTEREN:
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if (env->priv_ver >= PRIV_VERSION_1_10_0) {
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env->scounteren = val_to_write;
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break;
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} else {
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goto do_illegal;
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}
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case CSR_SSCRATCH:
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env->sscratch = val_to_write;
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break;
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case CSR_SCAUSE:
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env->scause = val_to_write;
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break;
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case CSR_SBADADDR:
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env->sbadaddr = val_to_write;
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break;
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case CSR_MEPC:
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env->mepc = val_to_write;
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break;
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case CSR_MTVEC:
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/* bits [1:0] indicate mode; 0 = direct, 1 = vectored, 2 >= reserved */
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if ((val_to_write & 3) == 0) {
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env->mtvec = val_to_write >> 2 << 2;
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} else {
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qemu_log_mask(LOG_UNIMP,
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"CSR_MTVEC: vectored traps not supported\n");
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}
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break;
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case CSR_MCOUNTEREN:
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if (env->priv_ver >= PRIV_VERSION_1_10_0) {
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env->mcounteren = val_to_write;
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break;
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} else {
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goto do_illegal;
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}
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case CSR_MSCRATCH:
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env->mscratch = val_to_write;
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break;
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case CSR_MCAUSE:
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env->mcause = val_to_write;
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break;
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case CSR_MBADADDR:
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env->mbadaddr = val_to_write;
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break;
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case CSR_MISA:
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/* misa is WARL so unsupported writes are ignored */
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break;
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case CSR_PMPCFG0:
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case CSR_PMPCFG1:
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case CSR_PMPCFG2:
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case CSR_PMPCFG3:
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pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val_to_write);
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break;
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case CSR_PMPADDR0:
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case CSR_PMPADDR1:
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case CSR_PMPADDR2:
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case CSR_PMPADDR3:
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case CSR_PMPADDR4:
|
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case CSR_PMPADDR5:
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case CSR_PMPADDR6:
|
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case CSR_PMPADDR7:
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case CSR_PMPADDR8:
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case CSR_PMPADDR9:
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case CSR_PMPADDR10:
|
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case CSR_PMPADDR11:
|
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case CSR_PMPADDR12:
|
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case CSR_PMPADDR13:
|
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case CSR_PMPADDR14:
|
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case CSR_PMPADDR15:
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pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val_to_write);
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break;
|
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#endif
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#if !defined(CONFIG_USER_ONLY)
|
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do_illegal:
|
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#endif
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default:
|
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do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
|
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}
|
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}
|
|
|
|
/*
|
|
* Handle reads to CSRs and any resulting special behavior
|
|
*
|
|
* Adapted from Spike's processor_t::get_csr
|
|
*/
|
|
target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
|
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{
|
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#ifndef CONFIG_USER_ONLY
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target_ulong ctr_en = env->priv == PRV_U ? env->scounteren :
|
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env->priv == PRV_S ? env->mcounteren : -1U;
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#else
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target_ulong ctr_en = -1;
|
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#endif
|
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target_ulong ctr_ok = (ctr_en >> (csrno & 31)) & 1;
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|
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if (csrno >= CSR_HPMCOUNTER3 && csrno <= CSR_HPMCOUNTER31) {
|
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if (ctr_ok) {
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return 0;
|
|
}
|
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}
|
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#if defined(TARGET_RISCV32)
|
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if (csrno >= CSR_HPMCOUNTER3H && csrno <= CSR_HPMCOUNTER31H) {
|
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if (ctr_ok) {
|
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return 0;
|
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}
|
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}
|
|
#endif
|
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if (csrno >= CSR_MHPMCOUNTER3 && csrno <= CSR_MHPMCOUNTER31) {
|
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return 0;
|
|
}
|
|
#if defined(TARGET_RISCV32)
|
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if (csrno >= CSR_MHPMCOUNTER3 && csrno <= CSR_MHPMCOUNTER31) {
|
|
return 0;
|
|
}
|
|
#endif
|
|
if (csrno >= CSR_MHPMEVENT3 && csrno <= CSR_MHPMEVENT31) {
|
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return 0;
|
|
}
|
|
|
|
switch (csrno) {
|
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case CSR_FFLAGS:
|
|
validate_mstatus_fs(env, GETPC());
|
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return cpu_riscv_get_fflags(env);
|
|
case CSR_FRM:
|
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validate_mstatus_fs(env, GETPC());
|
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return env->frm;
|
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case CSR_FCSR:
|
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validate_mstatus_fs(env, GETPC());
|
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return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
|
|
| (env->frm << FSR_RD_SHIFT);
|
|
/* rdtime/rdtimeh is trapped and emulated by bbl in system mode */
|
|
#ifdef CONFIG_USER_ONLY
|
|
case CSR_TIME:
|
|
return cpu_get_host_ticks();
|
|
#if defined(TARGET_RISCV32)
|
|
case CSR_TIMEH:
|
|
return cpu_get_host_ticks() >> 32;
|
|
#endif
|
|
#endif
|
|
case CSR_INSTRET:
|
|
case CSR_CYCLE:
|
|
if (ctr_ok) {
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
if (use_icount) {
|
|
return cpu_get_icount();
|
|
} else {
|
|
return cpu_get_host_ticks();
|
|
}
|
|
#else
|
|
return cpu_get_host_ticks();
|
|
#endif
|
|
}
|
|
break;
|
|
#if defined(TARGET_RISCV32)
|
|
case CSR_INSTRETH:
|
|
case CSR_CYCLEH:
|
|
if (ctr_ok) {
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
if (use_icount) {
|
|
return cpu_get_icount() >> 32;
|
|
} else {
|
|
return cpu_get_host_ticks() >> 32;
|
|
}
|
|
#else
|
|
return cpu_get_host_ticks() >> 32;
|
|
#endif
|
|
}
|
|
break;
|
|
#endif
|
|
#ifndef CONFIG_USER_ONLY
|
|
case CSR_MINSTRET:
|
|
case CSR_MCYCLE:
|
|
if (use_icount) {
|
|
return cpu_get_icount();
|
|
} else {
|
|
return cpu_get_host_ticks();
|
|
}
|
|
case CSR_MINSTRETH:
|
|
case CSR_MCYCLEH:
|
|
#if defined(TARGET_RISCV32)
|
|
if (use_icount) {
|
|
return cpu_get_icount() >> 32;
|
|
} else {
|
|
return cpu_get_host_ticks() >> 32;
|
|
}
|
|
#endif
|
|
break;
|
|
case CSR_MUCOUNTEREN:
|
|
if (env->priv_ver <= PRIV_VERSION_1_09_1) {
|
|
return env->scounteren;
|
|
} else {
|
|
break; /* illegal instruction */
|
|
}
|
|
case CSR_MSCOUNTEREN:
|
|
if (env->priv_ver <= PRIV_VERSION_1_09_1) {
|
|
return env->mcounteren;
|
|
} else {
|
|
break; /* illegal instruction */
|
|
}
|
|
case CSR_SSTATUS: {
|
|
target_ulong mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE
|
|
| SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS
|
|
| SSTATUS_SUM | SSTATUS_SD;
|
|
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
|
|
mask |= SSTATUS_MXR;
|
|
}
|
|
return env->mstatus & mask;
|
|
}
|
|
case CSR_SIP: {
|
|
qemu_mutex_lock_iothread();
|
|
target_ulong tmp = env->mip & env->mideleg;
|
|
qemu_mutex_unlock_iothread();
|
|
return tmp;
|
|
}
|
|
case CSR_SIE:
|
|
return env->mie & env->mideleg;
|
|
case CSR_SEPC:
|
|
return env->sepc;
|
|
case CSR_SBADADDR:
|
|
return env->sbadaddr;
|
|
case CSR_STVEC:
|
|
return env->stvec;
|
|
case CSR_SCOUNTEREN:
|
|
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
|
|
return env->scounteren;
|
|
} else {
|
|
break; /* illegal instruction */
|
|
}
|
|
case CSR_SCAUSE:
|
|
return env->scause;
|
|
case CSR_SATP: /* CSR_SPTBR */
|
|
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
|
|
return 0;
|
|
}
|
|
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
|
|
return env->satp;
|
|
} else {
|
|
return env->sptbr;
|
|
}
|
|
case CSR_SSCRATCH:
|
|
return env->sscratch;
|
|
case CSR_MSTATUS:
|
|
return env->mstatus;
|
|
case CSR_MIP: {
|
|
qemu_mutex_lock_iothread();
|
|
target_ulong tmp = env->mip;
|
|
qemu_mutex_unlock_iothread();
|
|
return tmp;
|
|
}
|
|
case CSR_MIE:
|
|
return env->mie;
|
|
case CSR_MEPC:
|
|
return env->mepc;
|
|
case CSR_MSCRATCH:
|
|
return env->mscratch;
|
|
case CSR_MCAUSE:
|
|
return env->mcause;
|
|
case CSR_MBADADDR:
|
|
return env->mbadaddr;
|
|
case CSR_MISA:
|
|
return env->misa;
|
|
case CSR_MARCHID:
|
|
return 0; /* as spike does */
|
|
case CSR_MIMPID:
|
|
return 0; /* as spike does */
|
|
case CSR_MVENDORID:
|
|
return 0; /* as spike does */
|
|
case CSR_MHARTID:
|
|
return env->mhartid;
|
|
case CSR_MTVEC:
|
|
return env->mtvec;
|
|
case CSR_MCOUNTEREN:
|
|
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
|
|
return env->mcounteren;
|
|
} else {
|
|
break; /* illegal instruction */
|
|
}
|
|
case CSR_MEDELEG:
|
|
return env->medeleg;
|
|
case CSR_MIDELEG:
|
|
return env->mideleg;
|
|
case CSR_PMPCFG0:
|
|
case CSR_PMPCFG1:
|
|
case CSR_PMPCFG2:
|
|
case CSR_PMPCFG3:
|
|
return pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
|
|
case CSR_PMPADDR0:
|
|
case CSR_PMPADDR1:
|
|
case CSR_PMPADDR2:
|
|
case CSR_PMPADDR3:
|
|
case CSR_PMPADDR4:
|
|
case CSR_PMPADDR5:
|
|
case CSR_PMPADDR6:
|
|
case CSR_PMPADDR7:
|
|
case CSR_PMPADDR8:
|
|
case CSR_PMPADDR9:
|
|
case CSR_PMPADDR10:
|
|
case CSR_PMPADDR11:
|
|
case CSR_PMPADDR12:
|
|
case CSR_PMPADDR13:
|
|
case CSR_PMPADDR14:
|
|
case CSR_PMPADDR15:
|
|
return pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
|
|
#endif
|
|
}
|
|
/* used by e.g. MTIME read */
|
|
do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
|
|
}
|
|
|
|
/*
|
|
* Check that CSR access is allowed.
|
|
*
|
|
* Adapted from Spike's decode.h:validate_csr
|
|
*/
|
|
static void validate_csr(CPURISCVState *env, uint64_t which,
|
|
uint64_t write, uintptr_t ra)
|
|
{
|
|
#ifndef CONFIG_USER_ONLY
|
|
unsigned csr_priv = get_field((which), 0x300);
|
|
unsigned csr_read_only = get_field((which), 0xC00) == 3;
|
|
if (((write) && csr_read_only) || (env->priv < csr_priv)) {
|
|
do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, ra);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
|
|
target_ulong csr)
|
|
{
|
|
validate_csr(env, csr, 1, GETPC());
|
|
uint64_t csr_backup = csr_read_helper(env, csr);
|
|
csr_write_helper(env, src, csr);
|
|
return csr_backup;
|
|
}
|
|
|
|
target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
|
|
target_ulong csr, target_ulong rs1_pass)
|
|
{
|
|
validate_csr(env, csr, rs1_pass != 0, GETPC());
|
|
uint64_t csr_backup = csr_read_helper(env, csr);
|
|
if (rs1_pass != 0) {
|
|
csr_write_helper(env, src | csr_backup, csr);
|
|
}
|
|
return csr_backup;
|
|
}
|
|
|
|
target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
|
|
target_ulong csr, target_ulong rs1_pass)
|
|
{
|
|
validate_csr(env, csr, rs1_pass != 0, GETPC());
|
|
uint64_t csr_backup = csr_read_helper(env, csr);
|
|
if (rs1_pass != 0) {
|
|
csr_write_helper(env, (~src) & csr_backup, csr);
|
|
}
|
|
return csr_backup;
|
|
}
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
|
|
{
|
|
if (!(env->priv >= PRV_S)) {
|
|
do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
|
|
}
|
|
|
|
target_ulong retpc = env->sepc;
|
|
if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
|
|
do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
|
|
}
|
|
|
|
target_ulong mstatus = env->mstatus;
|
|
target_ulong prev_priv = get_field(mstatus, MSTATUS_SPP);
|
|
mstatus = set_field(mstatus,
|
|
env->priv_ver >= PRIV_VERSION_1_10_0 ?
|
|
MSTATUS_SIE : MSTATUS_UIE << prev_priv,
|
|
get_field(mstatus, MSTATUS_SPIE));
|
|
mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
|
|
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
|
|
riscv_set_mode(env, prev_priv);
|
|
csr_write_helper(env, mstatus, CSR_MSTATUS);
|
|
|
|
return retpc;
|
|
}
|
|
|
|
target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
|
|
{
|
|
if (!(env->priv >= PRV_M)) {
|
|
do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
|
|
}
|
|
|
|
target_ulong retpc = env->mepc;
|
|
if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
|
|
do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
|
|
}
|
|
|
|
target_ulong mstatus = env->mstatus;
|
|
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
|
|
mstatus = set_field(mstatus,
|
|
env->priv_ver >= PRIV_VERSION_1_10_0 ?
|
|
MSTATUS_MIE : MSTATUS_UIE << prev_priv,
|
|
get_field(mstatus, MSTATUS_MPIE));
|
|
mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
|
|
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
|
|
riscv_set_mode(env, prev_priv);
|
|
csr_write_helper(env, mstatus, CSR_MSTATUS);
|
|
|
|
return retpc;
|
|
}
|
|
|
|
void helper_wfi(CPURISCVState *env)
|
|
{
|
|
CPUState *cs = CPU(riscv_env_get_cpu(env));
|
|
|
|
cs->halted = 1;
|
|
cs->exception_index = EXCP_HLT;
|
|
cpu_loop_exit(cs);
|
|
}
|
|
|
|
void helper_tlb_flush(CPURISCVState *env)
|
|
{
|
|
RISCVCPU *cpu = riscv_env_get_cpu(env);
|
|
CPUState *cs = CPU(cpu);
|
|
tlb_flush(cs);
|
|
}
|
|
|
|
#endif /* !CONFIG_USER_ONLY */
|