Peter Maydell 19bef037fe RISC-V Fixes for 4.2-rc2
This contains a handful of patches that I'd like to target for 4.2:
 
 * OpenSBI upgrade to 0.5
 * Increase in the flash size of the virt board.
 * A non-functional cleanup.
 * A cleanup to our MIP handling that avoids atomics.
 
 This passes "make check" and boots OpenEmbedded for me.
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Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc2' into staging

RISC-V Fixes for 4.2-rc2

This contains a handful of patches that I'd like to target for 4.2:

* OpenSBI upgrade to 0.5
* Increase in the flash size of the virt board.
* A non-functional cleanup.
* A cleanup to our MIP handling that avoids atomics.

This passes "make check" and boots OpenEmbedded for me.

# gpg: Signature made Thu 14 Nov 2019 18:39:27 GMT
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.2-rc2:
  riscv/virt: Increase flash size
  opensbi: Upgrade from v0.4 to v0.5
  target/riscv: Remove atomic accesses to MIP CSR
  remove unnecessary ifdef TARGET_RISCV64

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-11-15 11:22:33 +00:00
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2019-01-22 07:27:59 +01:00
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