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Original Xbox Emulator for Windows, macOS, and Linux (Active Development)
1cbdd96813
This patch introduces a few changes to how FIS packets are deciphered in the AHCI virtual device. The summary of changes can be grouped into two pieces: [A] Changes to how we apply a preliminary sieve to FISes, [B] Changes in how we internalize a decomposed FIS. == Changes to how we apply a preliminary sieve to FISes == (1) Packets may now either update the Control register or the Command register, but not both. This is according to the SATA 3.2 specification which states: "...the device either initiates processing of the command indicated in the Command register or initiates processing of the control request indicated [...] depending on the state of the C bit in the FIS." See SATA 3.2 section 10.5.5.4, "Reception" in the 10.5.5 "Register Host to Device FIS" section. This change accounts for the first two regions of change within the diff. All other changes belong to the following changes. == Changes in how we internalize a decomposed FIS == (2) Instead of trying to extract the sector number out of the FIS from bytes 4-10 and setting it with ide_set_sector, we set the appropriate IDEState registers and trust that ide_get_sector can retrieve the correct sector later. By "constructing" the sector for use with ide_set_sector, we are duplicating the mechanisms of ide_get_sector. This change makes the FIS decomposition more obvious. SATA 3.2 as a specification does not make the legacy register mapping with respect to the D2H FIS obvious. However, SATA 3.2 section 10.5.5.1 "Register Host to Device FIS layout" describes all of the "cmd_fis" bytes: 0 - FIS Type (0x27) 1 - Port Multiplier Port and Command Update flag 2 - ATA Command 3 - Features_Low 4 - LBA 7:0 5 - LBA 15:8 6 - LBA 23:16 7 - Device, AKA "Drive Select." 8 - LBA 31:24 9 - LBA 39:32 10 - LBA 47:40 11 - Features_High 12 - Count Low 13 - Count High 14 - ICC 15 - Control 16-19 - Auxiliary (for NCQ, defined per-command) Most of these registers map to existing IDEState registers in obvious ways, especially features, select, hob_features, and nsector (count). ICC is reserved in older specifications but is not supported in our implementation, and remains unused here. The Control register is not valid for a command that is trying to update the command register and is to be considered reserved at this point. What is not obvious is the LBA register mappings, but SATA 1.0 can help inform of us legacy device support, see SATA 1.0 section 8.5.2 "Register - Host to Device." LBA 7:0 - Sector Number (sector) LBA 15:8 - Cyl Low (lcyl) LBA 23:16 - Cyl High (hcyl) LBA 31:24 - Sector Num Exp. (hob_sector) LBA 39:32 - Cyl Low Exp. (hob_lcyl) LBA 47:40 - Cyl High Exp. (hob_hcyl) These mappings help guide which registers the FIS should be decomposed into/towards for CHS, LBA28 and LBA48 commands. As a note: The prior confusion that can be seen in the documentation arises from the fact that CHS and LBA28 commands use the low nybble of the drive select register to store LBA 27:24, whereas LNA48 commands use the hob_sector, hob_lcyl and hob_hcyl registers as explained above. The decomposition as it stands now will correctly decompose CHS, LBA28 and LBA48 commands into their appropriate registers where the core IDE/ATAPI layers can deal with them correctly. See the below point for more information. (3) We save cmd_fis[7] as ide_state->select, which informs decisions about if we are using LBA or CHS. This corrects a bug in AHCI wherein we attempt to set and/or retrieve the sector number by using ide_set_sector and ide_get_sector, which depend on the select register to determine if we are using LBA or CHS. Without this adjustment, LBA48 read/writes are currently broken. Thanks to Eniac Zheng @ HP for pointing this out. (4) Save cmd_fis[11] as ide_state->hob_feature, as defined in SATA 3.2. (5) For several ATA commands, the sector count register set to 0 is a magic number that means 256 sectors. For LBA48 commands, this means 65,536 sectors. We drop the magic sector correction here, and trust the ide core layer to handle the conversion appropriately, in ide_cmd_lba48_transform(). As it stands, the current AHCI code is only compliant with LBA28 commands. By simply removing the magic, it will work with LBA28 and LBA48. (6) We expand FIS decomposition to include both ATAPI and IDE devices. We leave the logic of determining if the fields are valid or not to the respective layers. This change intends to make it clearer that AHCI is only a composition mechanism for the FIS packets: the meanings of the registers is best left to the implementation layers for those devices. (7) Forcefully setting the feature, hcyl and lcyl registers for ATAPI commands is removed. - The hcyl and lcyl magic present here is valid at boot only, and should not be overridden for every PACKET command. - The feature register is defined as valid for the PACKET command, so we should not suppress it. The ATAPI layer does not even currently depend on or require 0x01 as mandatory. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1415058979-16604-3-git-send-email-jsnow@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> |
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audio | ||
backends | ||
block | ||
bsd-user | ||
default-configs | ||
disas | ||
docs | ||
dtc@bc895d6d09 | ||
fpu | ||
fsdev | ||
gdb-xml | ||
hw | ||
include | ||
libcacard | ||
libdecnumber | ||
linux-headers | ||
linux-user | ||
net | ||
pc-bios | ||
pixman@87eea99e44 | ||
po | ||
qapi | ||
qga | ||
qobject | ||
qom | ||
roms | ||
scripts | ||
slirp | ||
stubs | ||
sysconfigs/target | ||
target-alpha | ||
target-arm | ||
target-cris | ||
target-i386 | ||
target-lm32 | ||
target-m68k | ||
target-microblaze | ||
target-mips | ||
target-moxie | ||
target-openrisc | ||
target-ppc | ||
target-s390x | ||
target-sh4 | ||
target-sparc | ||
target-tricore | ||
target-unicore32 | ||
target-xtensa | ||
tcg | ||
tests | ||
trace | ||
ui | ||
util | ||
.exrc | ||
.gitignore | ||
.gitmodules | ||
.mailmap | ||
.travis.yml | ||
accel.c | ||
aio-posix.c | ||
aio-win32.c | ||
arch_init.c | ||
async.c | ||
balloon.c | ||
block-migration.c | ||
block.c | ||
blockdev-nbd.c | ||
blockdev.c | ||
blockjob.c | ||
bootdevice.c | ||
bt-host.c | ||
bt-vhci.c | ||
Changelog | ||
CODING_STYLE | ||
configure | ||
COPYING | ||
COPYING.LIB | ||
coroutine-gthread.c | ||
coroutine-sigaltstack.c | ||
coroutine-ucontext.c | ||
coroutine-win32.c | ||
cpu-exec.c | ||
cpus.c | ||
cputlb.c | ||
device_tree.c | ||
device-hotplug.c | ||
disas.c | ||
dma-helpers.c | ||
dump.c | ||
exec.c | ||
gdbstub.c | ||
HACKING | ||
hmp-commands.hx | ||
hmp.c | ||
hmp.h | ||
iohandler.c | ||
ioport.c | ||
iothread.c | ||
kvm-all.c | ||
kvm-stub.c | ||
LICENSE | ||
main-loop.c | ||
MAINTAINERS | ||
Makefile | ||
Makefile.objs | ||
Makefile.target | ||
memory_mapping.c | ||
memory.c | ||
migration-exec.c | ||
migration-fd.c | ||
migration-rdma.c | ||
migration-tcp.c | ||
migration-unix.c | ||
migration.c | ||
module-common.c | ||
monitor.c | ||
nbd.c | ||
numa.c | ||
os-posix.c | ||
os-win32.c | ||
page_cache.c | ||
qapi-schema.json | ||
qdev-monitor.c | ||
qdict-test-data.txt | ||
qemu-bridge-helper.c | ||
qemu-char.c | ||
qemu-coroutine-io.c | ||
qemu-coroutine-lock.c | ||
qemu-coroutine-sleep.c | ||
qemu-coroutine.c | ||
qemu-doc.texi | ||
qemu-file-stdio.c | ||
qemu-file-unix.c | ||
qemu-file.c | ||
qemu-img-cmds.hx | ||
qemu-img.c | ||
qemu-img.texi | ||
qemu-io-cmds.c | ||
qemu-io.c | ||
qemu-log.c | ||
qemu-nbd.c | ||
qemu-nbd.texi | ||
qemu-options-wrapper.h | ||
qemu-options.h | ||
qemu-options.hx | ||
qemu-seccomp.c | ||
qemu-tech.texi | ||
qemu-timer.c | ||
qemu.nsi | ||
qemu.sasl | ||
qmp-commands.hx | ||
qmp.c | ||
qtest.c | ||
README | ||
rules.mak | ||
savevm.c | ||
softmmu_template.h | ||
spice-qemu-char.c | ||
tcg-runtime.c | ||
tci.c | ||
thread-pool.c | ||
thunk.c | ||
tpm.c | ||
trace-events | ||
translate-all.c | ||
translate-all.h | ||
user-exec.c | ||
VERSION | ||
version.rc | ||
vl.c | ||
vmstate.c | ||
xbzrle.c | ||
xen-common-stub.c | ||
xen-common.c | ||
xen-hvm-stub.c | ||
xen-hvm.c | ||
xen-mapcache.c |
Read the documentation in qemu-doc.html or on http://wiki.qemu-project.org - QEMU team