Alistair Francis 2308092b2b hw/riscv/sifive_u: Create a SiFive U SoC object ...

Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine.

We leave the SoC, RAM, device tree and reset/fdt loading as part of the
machine. All the other device creation has been moved to the SoC.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>

2018-07-05 15:24:25 -07:00

..

riscv_hart.h

RISC-V HART Array

2018-03-07 08:30:28 +13:00

riscv_htif.h

…

sifive_clint.h

RISC-V: Replace hardcoded constants with enum values

2018-05-06 10:39:38 +12:00

sifive_e.h

RISC-V: Remove unused class definitions

2018-05-06 10:39:38 +12:00

sifive_plic.h

SiFive RISC-V PLIC Block

2018-03-07 08:30:28 +13:00

sifive_prci.h

SiFive RISC-V PRCI Block

2018-03-07 08:30:28 +13:00

sifive_test.h

SiFive RISC-V Test Finisher

2018-03-07 08:30:28 +13:00

sifive_u.h

hw/riscv/sifive_u: Create a SiFive U SoC object

2018-07-05 15:24:25 -07:00

sifive_uart.h

SiFive RISC-V UART Device

2018-03-07 08:30:28 +13:00

spike.h

RISC-V: Make some header guards more specific

2018-05-06 10:39:38 +12:00

virt.h

RISC-V: Make virt header comment title consistent

2018-05-06 10:39:38 +12:00