Kirill A. Shutemov 6c7c3c21f9 x86: implement la57 paging mode ... The new paging more is extension of IA32e mode with more additional page table level. It brings support of 57-bit vitrual address space (128PB) and 52-bit physical address space (4PB). The structure of new page table level is identical to pml4. The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16]. CR4.LA57[bit 12] need to be set when pageing enables to activate 5-level paging mode. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Message-Id: <20161215001305.146807-1-kirill.shutemov@linux.intel.com> [Drop changes to target-i386/translate.c. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2016-12-22 16:01:04 +01:00
..
alpha
arm
cris
i386	x86: implement la57 paging mode	2016-12-22 16:01:04 +01:00
lm32
m68k
microblaze
mips
moxie
openrisc
ppc
s390x
sh4
sparc
tilegx
tricore
unicore32
xtensa