xemu/target/mips
Lluís Vilanova 9c489ea6be tcg: Pass generic CPUState to gen_intermediate_code()
Needed to implement a target-agnostic gen_intermediate_code()
in the future.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Alex Benneé <alex.benee@linaro.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19 14:45:16 -07:00
..
cpu-qom.h
cpu.c qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
cpu.h target-mips: Provide function to test if a CPU supports an ISA 2017-02-21 22:24:58 +00:00
dsp_helper.c
gdbstub.c
helper.c mips: set CP0 Debug DExcCode for SDBBP instruction 2017-07-17 16:48:21 +02:00
helper.h target-mips: Use clz opcode 2017-01-10 08:06:11 -08:00
kvm_mips.h
kvm.c vcpu_dirty: share the same field in CPUState for all accelerators 2017-07-04 14:30:03 +02:00
lmi_helper.c
machine.c migration: extend VMStateInfo 2017-01-24 17:54:47 +00:00
Makefile.objs
mips-defs.h
mips-semi.c
msa_helper.c
op_helper.c target/mips: hold BQL for timer interrupts 2017-03-09 10:41:48 +00:00
TODO
trace-events target-mips: replace few LOG_DISAS() with trace points 2017-03-20 11:06:32 +00:00
translate_init.c
translate.c tcg: Pass generic CPUState to gen_intermediate_code() 2017-07-19 14:45:16 -07:00