xemu/target/openrisc
Lluís Vilanova 9c489ea6be tcg: Pass generic CPUState to gen_intermediate_code()
Needed to implement a target-agnostic gen_intermediate_code()
in the future.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Alex Benneé <alex.benee@linaro.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19 14:45:16 -07:00
..
cpu.c target/openrisc: Support non-busy idle state using PMR SPR 2017-05-04 09:39:14 +09:00
cpu.h target/openrisc: Support non-busy idle state using PMR SPR 2017-05-04 09:39:14 +09:00
exception_helper.c target/openrisc: Optimize for r0 being zero 2017-02-14 08:15:00 +11:00
exception.c
exception.h
fpu_helper.c target/openrisc: Fix madd 2017-02-14 08:15:00 +11:00
gdbstub.c target/openrisc: implement shadow registers 2017-05-04 09:39:01 +09:00
helper.h target/openrisc: Fix madd 2017-02-14 08:15:00 +11:00
interrupt_helper.c target/openrisc: Tidy ppc/npc implementation 2017-02-14 08:15:00 +11:00
interrupt.c target/openrisc: Support non-busy idle state using PMR SPR 2017-05-04 09:39:14 +09:00
machine.c target/openrisc: Support non-busy idle state using PMR SPR 2017-05-04 09:39:14 +09:00
Makefile.objs target/openrisc: Streamline arithmetic and OVE 2017-02-14 08:14:59 +11:00
mmu_helper.c
mmu.c target/openrisc: Fixes for memory debugging 2017-05-04 09:38:49 +09:00
sys_helper.c target/openrisc: Support non-busy idle state using PMR SPR 2017-05-04 09:39:14 +09:00
translate.c tcg: Pass generic CPUState to gen_intermediate_code() 2017-07-19 14:45:16 -07:00