xemu/hw/dma
Peter Maydell f00f57f344 This PR includes multiple fixes and features for RISC-V:
- Fixes a bug in printing trap causes
  - Allows 16-bit writes to the SiFive test device. This fixes the
    failure to reboot the RISC-V virt machine
  - Support for the Microchip PolarFire SoC and Icicle Kit
  - A reafactor of RISC-V code out of hw/riscv
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging

This PR includes multiple fixes and features for RISC-V:
 - Fixes a bug in printing trap causes
 - Allows 16-bit writes to the SiFive test device. This fixes the
   failure to reboot the RISC-V virt machine
 - Support for the Microchip PolarFire SoC and Icicle Kit
 - A reafactor of RISC-V code out of hw/riscv

# gpg: Signature made Thu 10 Sep 2020 19:08:06 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits)
  hw/riscv: Sort the Kconfig options in alphabetical order
  hw/riscv: Drop CONFIG_SIFIVE
  hw/riscv: Always build riscv_hart.c
  hw/riscv: Move sifive_test model to hw/misc
  hw/riscv: Move sifive_uart model to hw/char
  hw/riscv: Move riscv_htif model to hw/char
  hw/riscv: Move sifive_plic model to hw/intc
  hw/riscv: Move sifive_clint model to hw/intc
  hw/riscv: Move sifive_gpio model to hw/gpio
  hw/riscv: Move sifive_u_otp model to hw/misc
  hw/riscv: Move sifive_u_prci model to hw/misc
  hw/riscv: Move sifive_e_prci model to hw/misc
  hw/riscv: sifive_u: Connect a DMA controller
  hw/riscv: clint: Avoid using hard-coded timebase frequency
  hw/riscv: microchip_pfsoc: Hook GPIO controllers
  hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
  hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
  hw/net: cadence_gem: Add a new 'phy-addr' property
  hw/riscv: microchip_pfsoc: Connect a DMA controller
  hw/dma: Add SiFive platform DMA controller emulation
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

# Conflicts:
#	hw/riscv/trace-events
2020-09-13 20:29:35 +01:00
..
bcm2835_dma.c qom: Don't handle impossible object_property_get_link() failure 2020-07-10 15:18:08 +02:00
etraxfs_dma.c Remove unnecessary cast when using the cpu_[physical]_memory API 2020-02-20 14:47:08 +01:00
i8257.c i8257: Move QOM macro to header 2020-08-27 14:04:54 -04:00
i82374.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
Kconfig hw/dma: Add SiFive platform DMA controller emulation 2020-09-09 15:54:18 -07:00
meson.build hw/dma: Add SiFive platform DMA controller emulation 2020-09-09 15:54:18 -07:00
omap_dma.c hw/dma/omap_dma: Move switch 'fall through' comment to correct place 2019-08-21 10:55:23 +02:00
pl080.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
pl330.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
puv3_dma.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
pxa2xx_dma.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
rc4030.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
sifive_pdma.c hw/dma: Add SiFive platform DMA controller emulation 2020-09-09 15:54:18 -07:00
soc_dma.c misc: Replace zero-length arrays with flexible array member (automatic) 2020-03-16 22:07:42 +01:00
sparc32_dma.c esp: Rename ESP_STATE to ESP 2020-09-09 13:20:22 -04:00
trace-events dma/pl330: Convert to support tracing 2020-01-23 15:34:04 +00:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
xilinx_axidma.c xilinx_axidma: Use typedef name for instance_size 2020-09-09 13:20:22 -04:00
xlnx_dpdma.c util/hexdump: Reorder qemu_hexdump() arguments 2020-09-11 21:25:59 +02:00
xlnx-zdma.c qom: Drop parameter @errp of object_property_add() & friends 2020-05-15 07:07:58 +02:00
xlnx-zynq-devcfg.c Clean up inclusion of sysemu/sysemu.h 2019-08-16 13:31:53 +02:00