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f00f57f344
- Fixes a bug in printing trap causes - Allows 16-bit writes to the SiFive test device. This fixes the failure to reboot the RISC-V virt machine - Support for the Microchip PolarFire SoC and Icicle Kit - A reafactor of RISC-V code out of hw/riscv -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAl9aa4YACgkQIeENKd+X cFTJjgf5ASfFIO5HqP1l80/UM5Pswyq0IROZDq0ItZa6U4EPzLXoE2N0POriIj4h Ds2JbMg0ORDqY0VbSxHlgYHMgJ9S6cuVOMnATsPG0d2jaJ3gSxLBu5k/1ENqe+Vw sSYXZv5uEAUfOFz99zbuhKHct5HzlmBFW9dVHdflUQS+cRgsSXq27mz1BvZ8xMWl lMhwubqdoNx0rOD3vKnlwrxaf54DcJ2IQT3BtTCjEar3tukdNaLijAuwt2hrFyr+ IwpeFXA/NWar+mXP3M+BvcLaI33j73/ac2+S5SJuzHGp/ot5nT5gAuq3PDEjHMeS t6z9Exp776VXxNE2iUA5NB65Yp3/6w== =07oA -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging This PR includes multiple fixes and features for RISC-V: - Fixes a bug in printing trap causes - Allows 16-bit writes to the SiFive test device. This fixes the failure to reboot the RISC-V virt machine - Support for the Microchip PolarFire SoC and Icicle Kit - A reafactor of RISC-V code out of hw/riscv # gpg: Signature made Thu 10 Sep 2020 19:08:06 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits) hw/riscv: Sort the Kconfig options in alphabetical order hw/riscv: Drop CONFIG_SIFIVE hw/riscv: Always build riscv_hart.c hw/riscv: Move sifive_test model to hw/misc hw/riscv: Move sifive_uart model to hw/char hw/riscv: Move riscv_htif model to hw/char hw/riscv: Move sifive_plic model to hw/intc hw/riscv: Move sifive_clint model to hw/intc hw/riscv: Move sifive_gpio model to hw/gpio hw/riscv: Move sifive_u_otp model to hw/misc hw/riscv: Move sifive_u_prci model to hw/misc hw/riscv: Move sifive_e_prci model to hw/misc hw/riscv: sifive_u: Connect a DMA controller hw/riscv: clint: Avoid using hard-coded timebase frequency hw/riscv: microchip_pfsoc: Hook GPIO controllers hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 hw/net: cadence_gem: Add a new 'phy-addr' property hw/riscv: microchip_pfsoc: Connect a DMA controller hw/dma: Add SiFive platform DMA controller emulation ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/riscv/trace-events |
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.. | ||
can | ||
fsl_etsec | ||
rocker | ||
allwinner_emac.c | ||
allwinner-sun8i-emac.c | ||
cadence_gem.c | ||
dp8393x.c | ||
e1000_regs.h | ||
e1000.c | ||
e1000e_core.c | ||
e1000e_core.h | ||
e1000e.c | ||
e1000x_common.c | ||
e1000x_common.h | ||
eepro100.c | ||
etraxfs_eth.c | ||
ftgmac100.c | ||
i82596.c | ||
i82596.h | ||
imx_fec.c | ||
Kconfig | ||
lan9118.c | ||
lance.c | ||
lasi_i82596.c | ||
mcf_fec.c | ||
meson.build | ||
milkymist-minimac2.c | ||
mipsnet.c | ||
msf2-emac.c | ||
ne2000-isa.c | ||
ne2000-pci.c | ||
ne2000.c | ||
ne2000.h | ||
net_rx_pkt.c | ||
net_rx_pkt.h | ||
net_tx_pkt.c | ||
net_tx_pkt.h | ||
opencores_eth.c | ||
pcnet-pci.c | ||
pcnet.c | ||
pcnet.h | ||
rtl8139.c | ||
smc91c111.c | ||
spapr_llan.c | ||
stellaris_enet.c | ||
sungem.c | ||
sunhme.c | ||
trace-events | ||
trace.h | ||
tulip.c | ||
tulip.h | ||
vhost_net-stub.c | ||
vhost_net.c | ||
virtio-net.c | ||
vmware_utils.h | ||
vmxnet3_defs.h | ||
vmxnet3.c | ||
vmxnet3.h | ||
vmxnet_debug.h | ||
xen_nic.c | ||
xgmac.c | ||
xilinx_axienet.c | ||
xilinx_ethlite.c |