Alistair Francis fe0fe4735e riscv: Initial commit of OpenTitan machine ... This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>		2020-06-03 09:11:51 -07:00
..
boot.c	riscv: Change the default behavior if no -bios option is specified	2020-06-03 09:11:51 -07:00
Kconfig	riscv: Initial commit of OpenTitan machine	2020-06-03 09:11:51 -07:00
Makefile.objs	riscv: Initial commit of OpenTitan machine	2020-06-03 09:11:51 -07:00
opentitan.c	riscv: Initial commit of OpenTitan machine	2020-06-03 09:11:51 -07:00
riscv_hart.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
riscv_htif.c	chardev: Use QEMUChrEvent enum in IOEventHandler typedef	2020-01-08 11:15:35 +01:00
sifive_clint.c	hw/riscv: Provide rdtime callback for TCG in CLINT emulation	2020-02-27 13:46:37 -08:00
sifive_e_prci.c	riscv: sifive_e: prci: Update the PRCI register block size	2019-09-17 08:42:46 -07:00
sifive_e.c	riscv: sifive_e: Manually define the machine	2020-06-03 09:11:51 -07:00
sifive_gpio.c	Include migration/vmstate.h less	2019-08-16 13:31:52 +02:00
sifive_plic.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
sifive_test.c	riscv: hw: Remove the unnecessary include of target/riscv/cpu.h	2019-09-17 08:42:45 -07:00
sifive_u_otp.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
sifive_u_prci.c	riscv: sifive: Implement PRCI model for FU540	2019-09-17 08:42:47 -07:00
sifive_u.c	hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions	2020-06-03 09:11:51 -07:00
sifive_uart.c	chardev: Use QEMUChrEvent enum in IOEventHandler typedef	2020-01-08 11:15:35 +01:00
spike.c	hw/riscv: spike: Remove deprecated ISA specific machines	2020-06-03 09:11:51 -07:00
trace-events	SiFive RISC-V GPIO Device	2019-05-24 11:58:30 -07:00
virt.c	hw/riscv: virt: Remove the riscv_ prefix of the machine* functions	2020-06-03 09:11:51 -07:00