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3b2c52c017
- Add the '-noTSX' variants for CascadeLake and SkyLake.
- Document the three MSR bits: 'mds-no', 'taa-no', and 'tsx-ctrl'
Two confusing things about 'mds-no' (and the first point applies to
the other two MSRs too):
(1) The 'mds-no' bit will _not_ show up in the guest's /proc/cpuinfo.
Rather it is used to fill in the guest's sysfs:
/sys/devices/system/cpu/vulnerabilities/mds:Not affected
Paolo confirmed on IRC as such.
(2) There are _three_ variants[+] of CascadeLake CPUs, with different
stepping levels: 5, 6, and 7. To quote wikichip.org[*]:
"note that while steppings 6 & 7 are fully mitigated, earlier
stepping 5 is not protected against MSBDS, MLPDS, nor MDSUM"
The above is also indicated in the Intel's document[+], as
indicated by "No" under the three columns of MFBDS, MSBDS, and
MLPDS.
I've expressed this in the docs without belabouring the details.
[+] https://software.intel.com/security-software-guidance/insights/processors-affected-microarchitectural-data-sampling
[*] https://en.wikichip.org/wiki/intel/microarchitectures/cascade_lake#Key_changes_from_Skylake
Signed-off-by: Kashyap Chamarthy <kchamart@redhat.com>
Message-Id: <20200225165618.6571-3-kchamart@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
419 lines
14 KiB
PHP
419 lines
14 KiB
PHP
Recommendations for KVM CPU model configuration on x86 hosts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The information that follows provides recommendations for configuring
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CPU models on x86 hosts. The goals are to maximise performance, while
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protecting guest OS against various CPU hardware flaws, and optionally
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enabling live migration between hosts with heterogeneous CPU models.
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Two ways to configure CPU models with QEMU / KVM
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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(1) **Host passthrough**
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This passes the host CPU model features, model, stepping, exactly to
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the guest. Note that KVM may filter out some host CPU model features
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if they cannot be supported with virtualization. Live migration is
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unsafe when this mode is used as libvirt / QEMU cannot guarantee a
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stable CPU is exposed to the guest across hosts. This is the
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recommended CPU to use, provided live migration is not required.
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(2) **Named model**
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QEMU comes with a number of predefined named CPU models, that
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typically refer to specific generations of hardware released by
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Intel and AMD. These allow the guest VMs to have a degree of
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isolation from the host CPU, allowing greater flexibility in live
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migrating between hosts with differing hardware. @end table
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In both cases, it is possible to optionally add or remove individual CPU
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features, to alter what is presented to the guest by default.
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Libvirt supports a third way to configure CPU models known as "Host
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model". This uses the QEMU "Named model" feature, automatically picking
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a CPU model that is similar the host CPU, and then adding extra features
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to approximate the host model as closely as possible. This does not
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guarantee the CPU family, stepping, etc will precisely match the host
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CPU, as they would with "Host passthrough", but gives much of the
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benefit of passthrough, while making live migration safe.
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Preferred CPU models for Intel x86 hosts
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following CPU models are preferred for use on Intel hosts.
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Administrators / applications are recommended to use the CPU model that
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matches the generation of the host CPUs in use. In a deployment with a
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mixture of host CPU models between machines, if live migration
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compatibility is required, use the newest CPU model that is compatible
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across all desired hosts.
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``Cascadelake-Server``, ``Cascadelake-Server-noTSX``
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Intel Xeon Processor (Cascade Lake, 2019), with "stepping" levels 6
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or 7 only. (The Cascade Lake Xeon processor with *stepping 5 is
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vulnerable to MDS variants*.)
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``Skylake-Server``, ``Skylake-Server-IBRS``, ``Skylake-Server-IBRS-noTSX``
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Intel Xeon Processor (Skylake, 2016)
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``Skylake-Client``, ``Skylake-Client-IBRS``, ``Skylake-Client-noTSX-IBRS}``
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Intel Core Processor (Skylake, 2015)
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``Broadwell``, ``Broadwell-IBRS``, ``Broadwell-noTSX``, ``Broadwell-noTSX-IBRS``
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Intel Core Processor (Broadwell, 2014)
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``Haswell``, ``Haswell-IBRS``, ``Haswell-noTSX``, ``Haswell-noTSX-IBRS``
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Intel Core Processor (Haswell, 2013)
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``IvyBridge``, ``IvyBridge-IBR``
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Intel Xeon E3-12xx v2 (Ivy Bridge, 2012)
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``SandyBridge``, ``SandyBridge-IBRS``
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Intel Xeon E312xx (Sandy Bridge, 2011)
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``Westmere``, ``Westmere-IBRS``
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Westmere E56xx/L56xx/X56xx (Nehalem-C, 2010)
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``Nehalem``, ``Nehalem-IBRS``
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Intel Core i7 9xx (Nehalem Class Core i7, 2008)
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``Penryn``
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Intel Core 2 Duo P9xxx (Penryn Class Core 2, 2007)
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``Conroe``
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Intel Celeron_4x0 (Conroe/Merom Class Core 2, 2006)
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Important CPU features for Intel x86 hosts
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following are important CPU features that should be used on Intel
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x86 hosts, when available in the host CPU. Some of them require explicit
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configuration to enable, as they are not included by default in some, or
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all, of the named CPU models listed above. In general all of these
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features are included if using "Host passthrough" or "Host model".
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``pcid``
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Recommended to mitigate the cost of the Meltdown (CVE-2017-5754) fix.
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Included by default in Haswell, Broadwell & Skylake Intel CPU models.
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Should be explicitly turned on for Westmere, SandyBridge, and
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IvyBridge Intel CPU models. Note that some desktop/mobile Westmere
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CPUs cannot support this feature.
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``spec-ctrl``
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Required to enable the Spectre v2 (CVE-2017-5715) fix.
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Included by default in Intel CPU models with -IBRS suffix.
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Must be explicitly turned on for Intel CPU models without -IBRS
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suffix.
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Requires the host CPU microcode to support this feature before it
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can be used for guest CPUs.
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``stibp``
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Required to enable stronger Spectre v2 (CVE-2017-5715) fixes in some
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operating systems.
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Must be explicitly turned on for all Intel CPU models.
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Requires the host CPU microcode to support this feature before it can
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be used for guest CPUs.
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``ssbd``
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Required to enable the CVE-2018-3639 fix.
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Not included by default in any Intel CPU model.
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Must be explicitly turned on for all Intel CPU models.
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Requires the host CPU microcode to support this feature before it
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can be used for guest CPUs.
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``pdpe1gb``
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Recommended to allow guest OS to use 1GB size pages.
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Not included by default in any Intel CPU model.
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Should be explicitly turned on for all Intel CPU models.
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Note that not all CPU hardware will support this feature.
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``md-clear``
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Required to confirm the MDS (CVE-2018-12126, CVE-2018-12127,
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CVE-2018-12130, CVE-2019-11091) fixes.
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Not included by default in any Intel CPU model.
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Must be explicitly turned on for all Intel CPU models.
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Requires the host CPU microcode to support this feature before it
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can be used for guest CPUs.
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``mds-no``
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Recommended to inform the guest OS that the host is *not* vulnerable
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to any of the MDS variants ([MFBDS] CVE-2018-12130, [MLPDS]
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CVE-2018-12127, [MSBDS] CVE-2018-12126).
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This is an MSR (Model-Specific Register) feature rather than a CPUID feature,
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so it will not appear in the Linux ``/proc/cpuinfo`` in the host or
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guest. Instead, the host kernel uses it to populate the MDS
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vulnerability file in ``sysfs``.
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So it should only be enabled for VMs if the host reports @code{Not
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affected} in the ``/sys/devices/system/cpu/vulnerabilities/mds`` file.
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``taa-no``
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Recommended to inform that the guest that the host is ``not``
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vulnerable to CVE-2019-11135, TSX Asynchronous Abort (TAA).
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This too is an MSR feature, so it does not show up in the Linux
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``/proc/cpuinfo`` in the host or guest.
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It should only be enabled for VMs if the host reports ``Not affected``
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in the ``/sys/devices/system/cpu/vulnerabilities/tsx_async_abort``
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file.
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``tsx-ctrl``
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Recommended to inform the guest that it can disable the Intel TSX
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(Transactional Synchronization Extensions) feature; or, if the
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processor is vulnerable, use the Intel VERW instruction (a
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processor-level instruction that performs checks on memory access) as
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a mitigation for the TAA vulnerability. (For details, refer to
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Intel's `deep dive into MDS
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<https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling>`_.)
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Expose this to the guest OS if and only if: (a) the host has TSX
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enabled; *and* (b) the guest has ``rtm`` CPU flag enabled.
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By disabling TSX, KVM-based guests can avoid paying the price of
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mitigating TSX-based attacks.
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Note that ``tsx-ctrl`` too is an MSR feature, so it does not show
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up in the Linux ``/proc/cpuinfo`` in the host or guest.
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To validate that Intel TSX is indeed disabled for the guest, there are
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two ways: (a) check for the *absence* of ``rtm`` in the guest's
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``/proc/cpuinfo``; or (b) the
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``/sys/devices/system/cpu/vulnerabilities/tsx_async_abort`` file in
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the guest should report ``Mitigation: TSX disabled``.
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Preferred CPU models for AMD x86 hosts
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following CPU models are preferred for use on Intel hosts.
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Administrators / applications are recommended to use the CPU model that
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matches the generation of the host CPUs in use. In a deployment with a
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mixture of host CPU models between machines, if live migration
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compatibility is required, use the newest CPU model that is compatible
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across all desired hosts.
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``EPYC``, ``EPYC-IBPB``
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AMD EPYC Processor (2017)
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``Opteron_G5``
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AMD Opteron 63xx class CPU (2012)
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``Opteron_G4``
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AMD Opteron 62xx class CPU (2011)
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``Opteron_G3``
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AMD Opteron 23xx (Gen 3 Class Opteron, 2009)
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``Opteron_G2``
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AMD Opteron 22xx (Gen 2 Class Opteron, 2006)
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``Opteron_G1``
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AMD Opteron 240 (Gen 1 Class Opteron, 2004)
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Important CPU features for AMD x86 hosts
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following are important CPU features that should be used on AMD x86
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hosts, when available in the host CPU. Some of them require explicit
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configuration to enable, as they are not included by default in some, or
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all, of the named CPU models listed above. In general all of these
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features are included if using "Host passthrough" or "Host model".
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``ibpb``
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Required to enable the Spectre v2 (CVE-2017-5715) fix.
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Included by default in AMD CPU models with -IBPB suffix.
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Must be explicitly turned on for AMD CPU models without -IBPB suffix.
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Requires the host CPU microcode to support this feature before it
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can be used for guest CPUs.
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``stibp``
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Required to enable stronger Spectre v2 (CVE-2017-5715) fixes in some
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operating systems.
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Must be explicitly turned on for all AMD CPU models.
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Requires the host CPU microcode to support this feature before it
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can be used for guest CPUs.
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``virt-ssbd``
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Required to enable the CVE-2018-3639 fix
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Not included by default in any AMD CPU model.
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Must be explicitly turned on for all AMD CPU models.
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This should be provided to guests, even if amd-ssbd is also provided,
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for maximum guest compatibility.
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Note for some QEMU / libvirt versions, this must be force enabled when
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when using "Host model", because this is a virtual feature that
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doesn't exist in the physical host CPUs.
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``amd-ssbd``
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Required to enable the CVE-2018-3639 fix
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Not included by default in any AMD CPU model.
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Must be explicitly turned on for all AMD CPU models.
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This provides higher performance than ``virt-ssbd`` so should be
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exposed to guests whenever available in the host. ``virt-ssbd`` should
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none the less also be exposed for maximum guest compatibility as some
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kernels only know about ``virt-ssbd``.
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``amd-no-ssb``
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Recommended to indicate the host is not vulnerable CVE-2018-3639
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Not included by default in any AMD CPU model.
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Future hardware generations of CPU will not be vulnerable to
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CVE-2018-3639, and thus the guest should be told not to enable
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its mitigations, by exposing amd-no-ssb. This is mutually
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exclusive with virt-ssbd and amd-ssbd.
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``pdpe1gb``
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Recommended to allow guest OS to use 1GB size pages
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Not included by default in any AMD CPU model.
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Should be explicitly turned on for all AMD CPU models.
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Note that not all CPU hardware will support this feature.
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Default x86 CPU models
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^^^^^^^^^^^^^^^^^^^^^^
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The default QEMU CPU models are designed such that they can run on all
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hosts. If an application does not wish to do perform any host
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compatibility checks before launching guests, the default is guaranteed
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to work.
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The default CPU models will, however, leave the guest OS vulnerable to
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various CPU hardware flaws, so their use is strongly discouraged.
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Applications should follow the earlier guidance to setup a better CPU
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configuration, with host passthrough recommended if live migration is
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not needed.
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``qemu32``, ``qemu64``
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QEMU Virtual CPU version 2.5+ (32 & 64 bit variants)
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``qemu64`` is used for x86_64 guests and ``qemu32`` is used for i686
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guests, when no ``-cpu`` argument is given to QEMU, or no ``<cpu>`` is
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provided in libvirt XML.
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Other non-recommended x86 CPUs
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following CPUs models are compatible with most AMD and Intel x86
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hosts, but their usage is discouraged, as they expose a very limited
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featureset, which prevents guests having optimal performance.
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``kvm32``, ``kvm64``
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Common KVM processor (32 & 64 bit variants).
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Legacy models just for historical compatibility with ancient QEMU
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versions.
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``486``, ``athlon``, ``phenom``, ``coreduo``, ``core2duo``, ``n270``, ``pentium``, ``pentium2``, ``pentium3``
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Various very old x86 CPU models, mostly predating the introduction
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of hardware assisted virtualization, that should thus not be
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required for running virtual machines.
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Syntax for configuring CPU models
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The examples below illustrate the approach to configuring the various
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CPU models / features in QEMU and libvirt.
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QEMU command line
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^^^^^^^^^^^^^^^^^
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Host passthrough:
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.. parsed-literal::
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|qemu_system| -cpu host
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Host passthrough with feature customization:
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.. parsed-literal::
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|qemu_system| -cpu host,-vmx,...
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Named CPU models:
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.. parsed-literal::
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|qemu_system| -cpu Westmere
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Named CPU models with feature customization:
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.. parsed-literal::
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|qemu_system| -cpu Westmere,+pcid,...
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Libvirt guest XML
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^^^^^^^^^^^^^^^^^
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Host passthrough::
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<cpu mode='host-passthrough'/>
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Host passthrough with feature customization::
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<cpu mode='host-passthrough'>
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<feature name="vmx" policy="disable"/>
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...
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</cpu>
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Host model::
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<cpu mode='host-model'/>
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Host model with feature customization::
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<cpu mode='host-model'>
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<feature name="vmx" policy="disable"/>
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...
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</cpu>
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Named model::
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<cpu mode='custom'>
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<model name="Westmere"/>
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</cpu>
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Named model with feature customization::
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<cpu mode='custom'>
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<model name="Westmere"/>
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<feature name="pcid" policy="require"/>
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...
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</cpu>
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