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2c047956f3
it fixes IRQ storm since guest isn't able to lower SCI IRQ after it has been handled when it clears GPE event. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
237 lines
7.6 KiB
C
237 lines
7.6 KiB
C
/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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* Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
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*
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* This is based on acpi.c.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "hw/hw.h"
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#include "qapi/visitor.h"
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#include "hw/i386/pc.h"
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#include "hw/pci/pci.h"
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#include "qemu/timer.h"
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#include "sysemu/sysemu.h"
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#include "hw/acpi/acpi.h"
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#include "sysemu/kvm.h"
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#include "exec/address-spaces.h"
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#include "hw/i386/ich9.h"
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//#define DEBUG
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#ifdef DEBUG
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#define ICH9_DEBUG(fmt, ...) \
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do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
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#else
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#define ICH9_DEBUG(fmt, ...) do { } while (0)
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#endif
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static void ich9_pm_update_sci_fn(ACPIREGS *regs)
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{
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ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
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acpi_update_sci(&pm->acpi_regs, pm->irq);
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}
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static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width)
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{
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ICH9LPCPMRegs *pm = opaque;
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return acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
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}
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static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
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unsigned width)
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{
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ICH9LPCPMRegs *pm = opaque;
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acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
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acpi_update_sci(&pm->acpi_regs, pm->irq);
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}
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static const MemoryRegionOps ich9_gpe_ops = {
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.read = ich9_gpe_readb,
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.write = ich9_gpe_writeb,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.impl.min_access_size = 1,
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.impl.max_access_size = 1,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width)
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{
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ICH9LPCPMRegs *pm = opaque;
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switch (addr) {
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case 0:
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return pm->smi_en;
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case 4:
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return pm->smi_sts;
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default:
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return 0;
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}
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}
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static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val,
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unsigned width)
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{
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ICH9LPCPMRegs *pm = opaque;
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switch (addr) {
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case 0:
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pm->smi_en = val;
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break;
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}
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}
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static const MemoryRegionOps ich9_smi_ops = {
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.read = ich9_smi_readl,
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.write = ich9_smi_writel,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
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{
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ICH9_DEBUG("to 0x%x\n", pm_io_base);
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assert((pm_io_base & ICH9_PMIO_MASK) == 0);
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pm->pm_io_base = pm_io_base;
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memory_region_transaction_begin();
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memory_region_set_enabled(&pm->io, pm->pm_io_base != 0);
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memory_region_set_address(&pm->io, pm->pm_io_base);
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memory_region_transaction_commit();
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}
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static int ich9_pm_post_load(void *opaque, int version_id)
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{
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ICH9LPCPMRegs *pm = opaque;
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uint32_t pm_io_base = pm->pm_io_base;
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pm->pm_io_base = 0;
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ich9_pm_iospace_update(pm, pm_io_base);
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return 0;
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}
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#define VMSTATE_GPE_ARRAY(_field, _state) \
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{ \
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.name = (stringify(_field)), \
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.version_id = 0, \
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.num = ICH9_PMIO_GPE0_LEN, \
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.info = &vmstate_info_uint8, \
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.size = sizeof(uint8_t), \
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.flags = VMS_ARRAY | VMS_POINTER, \
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.offset = vmstate_offset_pointer(_state, _field, uint8_t), \
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}
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const VMStateDescription vmstate_ich9_pm = {
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.name = "ich9_pm",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = ich9_pm_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
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VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
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VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
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VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs),
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VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
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VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
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VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
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VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
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VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
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VMSTATE_END_OF_LIST()
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}
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};
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static void pm_reset(void *opaque)
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{
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ICH9LPCPMRegs *pm = opaque;
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ich9_pm_iospace_update(pm, 0);
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acpi_pm1_evt_reset(&pm->acpi_regs);
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acpi_pm1_cnt_reset(&pm->acpi_regs);
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acpi_pm_tmr_reset(&pm->acpi_regs);
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acpi_gpe_reset(&pm->acpi_regs);
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if (kvm_enabled()) {
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/* Mark SMM as already inited to prevent SMM from running. KVM does not
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* support SMM mode. */
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pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
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}
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acpi_update_sci(&pm->acpi_regs, pm->irq);
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}
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static void pm_powerdown_req(Notifier *n, void *opaque)
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{
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ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);
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acpi_pm1_evt_power_down(&pm->acpi_regs);
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}
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void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
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qemu_irq sci_irq)
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{
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memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
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memory_region_set_enabled(&pm->io, false);
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memory_region_add_subregion(pci_address_space_io(lpc_pci),
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0, &pm->io);
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acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
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acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
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acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, 2);
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acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
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memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm,
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"apci-gpe0", ICH9_PMIO_GPE0_LEN);
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memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);
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memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm,
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"apci-smi", 8);
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memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
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pm->irq = sci_irq;
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qemu_register_reset(pm_reset, pm);
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pm->powerdown_notifier.notify = pm_powerdown_req;
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qemu_register_powerdown_notifier(&pm->powerdown_notifier);
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}
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static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v,
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void *opaque, const char *name,
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Error **errp)
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{
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ICH9LPCPMRegs *pm = opaque;
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uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS;
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visit_type_uint32(v, &value, name, errp);
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}
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void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp)
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{
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static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
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object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
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&pm->pm_io_base, errp);
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object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32",
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ich9_pm_get_gpe0_blk,
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NULL, NULL, pm, NULL);
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object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
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&gpe0_len, errp);
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}
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